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| author | Ben Skeggs <bskeggs@redhat.com> | 2010-03-29 10:06:09 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2010-04-09 10:15:38 +1000 |
| commit | 6f335a7afa6bc57603f39430dc6f9e57de288a91 (patch) | |
| tree | 38b0a878a6272ebb22bf43ec296195e267b3a540 /drivers/gpu/drm/nouveau/nv50_sor.c | |
| parent | d327dd4e771b5820743aeba0622116c5c8806388 (diff) | |
| download | linux-6f335a7afa6bc57603f39430dc6f9e57de288a91.tar.bz2 | |
drm/nv50: preserve an unknown SOR_MODECTRL value for DP encoders
This value interacts with some registers we don't currently know how to
program properly ourselves. The default of 5 that we were using matches
what the VBIOS on early DP cards do, but later ones use 6, which would
cause nouveau to program an incorrect mode on these chips.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_sor.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv50_sor.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c index c2fff543b06f..e31ba312c2ff 100644 --- a/drivers/gpu/drm/nouveau/nv50_sor.c +++ b/drivers/gpu/drm/nouveau/nv50_sor.c @@ -211,7 +211,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, mode_ctl = 0x0200; break; case OUTPUT_DP: - mode_ctl |= 0x00050000; + mode_ctl |= (nv_encoder->dp.mc_unknown << 16); if (nv_encoder->dcb->sorconf.link & 1) mode_ctl |= 0x00000800; else @@ -274,6 +274,7 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = { int nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) { + struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_encoder *nv_encoder = NULL; struct drm_encoder *encoder; bool dum; @@ -319,5 +320,24 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) encoder->possible_crtcs = entry->heads; encoder->possible_clones = 0; + if (nv_encoder->dcb->type == OUTPUT_DP) { + uint32_t mc, or = nv_encoder->or; + + if (dev_priv->chipset < 0x90 || + dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0) + mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or)); + else + mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or)); + + switch ((mc & 0x00000f00) >> 8) { + case 8: + case 9: + nv_encoder->dp.mc_unknown = (mc & 0x000f0000) >> 16; + break; + default: + break; + } + } + return 0; } |