Merge remote branch 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next into drm-fixes

* 'nouveau/for-airlied' of /ssd/git/drm-nouveau-next: (25 commits)
  nouveau: Acknowledge HPD irq in handler, not bottom half
  drm/nouveau: Fix a few confusions between "chipset" and "card_type".
  drm/nouveau: don't expose backlight control when available through ACPI
  drm/nouveau/pm: improve memtiming mappings
  drm/nouveau: Make PCIE GART size depend on the available RAMIN space.
  drm/nouveau: Return error from nouveau_gpuobj_new if we're out of RAMIN.
  drm/nouveau: Fix compilation issues in nouveau_pm when CONFIG_HWMON is not set
  drm/nouveau: Don't use load detection for connector polling.
  drm/nv10-nv20: Fix instability after MPLL changes.
  drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hang
  drm/nouveau: Don't poll LVDS outputs.
  drm/nouveau: Use "force" to decide if analog load detection is ok or not.
  drm/nv04: Fix scanout over the 16MB mark.
  drm/nouveau: fix nv40 pcie gart size
  drm/nva3: fix overflow in fixed point math used for pll calculation
  drm/nv10: Balance RTs expected to be accessed simultaneously by the 3d engine.
  drm/nouveau: Expose some BO usage flags to userspace.
  drm/nouveau: Reduce severity of the unknown getparam error.
  drm/nouveau: Avoid lock dependency between ramht and ramin spinlocks.
  drm/nouveau: Some random cleanups.
  ...

1 files changed, 21 insertions, 15 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 5c4c929d7f74..9a1fdcf400c2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -107,23 +107,29 @@ nouveau_gem_info(struct drm_gem_object *gem, struct drm_nouveau_gem_info *rep)
 }
 
 static bool
-nouveau_gem_tile_flags_valid(struct drm_device *dev, uint32_t tile_flags) {
-	switch (tile_flags) {
-	case 0x0000:
-	case 0x1800:
-	case 0x2800:
-	case 0x4800:
-	case 0x7000:
-	case 0x7400:
-	case 0x7a00:
-	case 0xe000:
-		break;
-	default:
-		NV_ERROR(dev, "bad page flags: 0x%08x\n", tile_flags);
-		return false;
+nouveau_gem_tile_flags_valid(struct drm_device *dev, uint32_t tile_flags)
+{
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+	if (dev_priv->card_type >= NV_50) {
+		switch (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) {
+		case 0x0000:
+		case 0x1800:
+		case 0x2800:
+		case 0x4800:
+		case 0x7000:
+		case 0x7400:
+		case 0x7a00:
+		case 0xe000:
+			return true;
+		}
+	} else {
+		if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
+			return true;
 	}
 
-	return true;
+	NV_ERROR(dev, "bad page flags: 0x%08x\n", tile_flags);
+	return false;
 }
 
 int