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| author | Stephane Viau <sviau@codeaurora.org> | 2015-01-27 11:35:56 -0500 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2015-04-01 19:29:33 -0400 |
| commit | a73f3382dae242261338588d8411057938501701 (patch) | |
| tree | 810e2ff10da3a12bcfc160a3598dd72862fa34e2 /drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | |
| parent | 034c5150ae8777265f5beae257f8e7f2721ebccc (diff) | |
| download | linux-a73f3382dae242261338588d8411057938501701.tar.bz2 | |
drm/msm/mdp5: only flush on a CRTC ->atomic_flush()
MDP5 hardware has some limitation and requires to avoid flushing
registers more than once between two Vblanks.
This change removes all FLUSH operations (except for HW cursor)
beside the one coming from a CRTC's ->atomic_flush().
This avoid this type of behavior (eg: CRTC + 1 plane overlay):
[drm:mdp5_crtc_vblank_irq] vblank
[drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0
[drm:mdp5_ctl_commit] flush (20040) CTL + LM0
[drm:mdp5_crtc_vblank_irq] blank
[drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0
[drm:mdp5_crtc_vblank_irq] blank
and replaces it by:
[drm:mdp5_crtc_vblank_irq] vblank
[drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0
[drm:mdp5_crtc_vblank_irq] blank
[drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0
[drm:mdp5_crtc_vblank_irq] blank
Only *one* FLUSH is called between Vblanks interrupts.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h')
0 files changed, 0 insertions, 0 deletions