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| author | Neil Armstrong <narmstrong@baylibre.com> | 2017-04-04 14:15:29 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2017-04-04 17:49:31 +0200 |
| commit | 2021d5b7d9f404bcb91301ececdf09a68b856ad7 (patch) | |
| tree | 5e736d1f31a9a00ca71f87adb342bc98482dfb6d /drivers/gpu/drm/meson/meson_vclk.c | |
| parent | 8cceda5349377e30cee5550acd41fefdd79d4ac6 (diff) | |
| download | linux-2021d5b7d9f404bcb91301ececdf09a68b856ad7.tar.bz2 | |
drm/meson: Convert existing documentation to actual kerneldoc
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/gpu/drm/meson/meson_vclk.c')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_vclk.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index 3731479746ca..47677047e42d 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -23,21 +23,29 @@ #include "meson_drv.h" #include "meson_vclk.h" -/* +/** + * DOC: Video Clocks + * * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL. * We handle the following encodings : + * * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks * - HDMI Pixel Clocks generation + * * What is missing : + * * - Genenate Pixel clocks for 2K/4K 10bit formats * * Clock generator scheme : - * __________ _________ _____ - * | | | | | |--ENCI - * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL - * |__________| |_________| \ | MUX |--ENCP - * --VCLK2-| |--VDAC - * |_____|--HDMI-TX + * + * .. code:: + * + * __________ _________ _____ + * | | | | | |--ENCI + * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL + * |__________| |_________| \ | MUX |--ENCP + * --VCLK2-| |--VDAC + * |_____|--HDMI-TX * * Final clocks can take input for either VCLK or VCLK2, but * VCLK is the preferred path for HDMI clocking and VCLK2 is the |