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authorJitao Shi <jitao.shi@mediatek.com>2019-08-11 18:40:05 +0800
committerCK Hu <ck.hu@mediatek.com>2019-10-07 12:29:38 +0800
commit7bf54afec961504d9618074539ec9ae2b8de8554 (patch)
treed081a06afdaee4088dfa343923feea91ee905cf7 /drivers/gpu/drm/mediatek
parent3c6bd94d32c45d47a0fce49e9cd64d72ff612bb5 (diff)
downloadlinux-7bf54afec961504d9618074539ec9ae2b8de8554.tar.bz2
drm/mediatek: add frame size control
Our new DSI chip has frame size control. So add the driver data to control for different chips. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
Diffstat (limited to 'drivers/gpu/drm/mediatek')
-rw-r--r--drivers/gpu/drm/mediatek/mtk_dsi.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 881c0afabf17..ac1a24035fef 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -72,6 +72,7 @@
#define DSI_VBP_NL 0x24
#define DSI_VFP_NL 0x28
#define DSI_VACT_NL 0x2C
+#define DSI_SIZE_CON 0x38
#define DSI_HSA_WC 0x50
#define DSI_HBP_WC 0x54
#define DSI_HFP_WC 0x58
@@ -156,6 +157,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+ bool has_size_ctl;
};
struct mtk_dsi {
@@ -424,6 +426,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
+ if (dsi->driver_data->has_size_ctl)
+ writel(vm->vactive << 16 | vm->hactive,
+ dsi->regs + DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)