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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-11-28 22:10:38 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-28 22:47:41 +0100
commit32cf0cb0294814cb1ee5d8727e9aac0e9aa80d2e (patch)
tree287d2d26b1186c11fa52f3588cbb0bd9adf4040f /drivers/gpu/drm/i915
parent3b32a35b31b19c8f9340d3b3a149062fce1cd89f (diff)
downloadlinux-32cf0cb0294814cb1ee5d8727e9aac0e9aa80d2e.tar.bz2
drm/i915: Fix pipe CSC post offset calculation
We were miscalculating the pipe CSC post offset for the full->limited range conversion. The resulting post offset was double what it was supposed to be, which caused blacks to come out grey when using limited range output on HSW+. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71769 Cc: stable@vger.kernel.org Tested-by: Lauri Mylläri <lauri.myllari@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d9369578fde..898bd98c96ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5815,7 +5815,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
uint16_t postoff = 0;
if (intel_crtc->config.limited_color_range)
- postoff = (16 * (1 << 13) / 255) & 0x1fff;
+ postoff = (16 * (1 << 12) / 255) & 0x1fff;
I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);