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| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2019-03-25 14:49:36 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-03-26 20:16:13 +0000 |
| commit | a2b4abfc626b13d2f2728f11435c8f3c4b9b39d8 (patch) | |
| tree | 1739d2f8009a07b79c9b7c7cadbba90a68394979 /drivers/gpu/drm/i915/intel_uncore.c | |
| parent | eb17af67eb1e2c57cc4fff9f59982d0ce6e9c802 (diff) | |
| download | linux-a2b4abfc626b13d2f2728f11435c8f3c4b9b39d8.tar.bz2 | |
drm/i915: switch uncore mmio funcs to use intel_uncore
The full read/write ops can now work on the intel_uncore struct.
Introduce intel_uncore_read/write functions working on intel_uncore
and switch the I915_READ/WRITE macro to internally call those.
v2: no change
v3: add intel_uncore_read/write functions (Chris), update commit msg
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-6-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uncore.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_uncore.c | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 78e4d5f2320e..7b7708506d64 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1093,7 +1093,6 @@ unclaimed_reg_debug(struct intel_uncore *uncore, } #define GEN2_READ_HEADER(x) \ - struct intel_uncore *uncore = &dev_priv->uncore; \ u##x val = 0; \ __assert_rpm_wakelock_held(uncore->rpm); @@ -1103,7 +1102,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore, #define __gen2_read(x) \ static u##x \ -gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ +gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ GEN2_READ_HEADER(x); \ val = __raw_uncore_read##x(uncore, reg); \ GEN2_READ_FOOTER; \ @@ -1111,7 +1110,7 @@ gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ #define __gen5_read(x) \ static u##x \ -gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ +gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ GEN2_READ_HEADER(x); \ ilk_dummy_write(uncore); \ val = __raw_uncore_read##x(uncore, reg); \ @@ -1134,7 +1133,6 @@ __gen2_read(64) #undef GEN2_READ_HEADER #define GEN6_READ_HEADER(x) \ - struct intel_uncore *uncore = &dev_priv->uncore; \ u32 offset = i915_mmio_reg_offset(reg); \ unsigned long irqflags; \ u##x val = 0; \ @@ -1178,7 +1176,7 @@ static inline void __force_wake_auto(struct intel_uncore *uncore, #define __gen_read(func, x) \ static u##x \ -func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ +func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ enum forcewake_domains fw_engine; \ GEN6_READ_HEADER(x); \ fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \ @@ -1211,7 +1209,6 @@ __gen6_read(64) #undef GEN6_READ_HEADER #define GEN2_WRITE_HEADER \ - struct intel_uncore *uncore = &dev_priv->uncore; \ trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ __assert_rpm_wakelock_held(uncore->rpm); \ @@ -1219,7 +1216,7 @@ __gen6_read(64) #define __gen2_write(x) \ static void \ -gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ +gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ GEN2_WRITE_HEADER; \ __raw_uncore_write##x(uncore, reg, val); \ GEN2_WRITE_FOOTER; \ @@ -1227,7 +1224,7 @@ gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool #define __gen5_write(x) \ static void \ -gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ +gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ GEN2_WRITE_HEADER; \ ilk_dummy_write(uncore); \ __raw_uncore_write##x(uncore, reg, val); \ @@ -1248,7 +1245,6 @@ __gen2_write(32) #undef GEN2_WRITE_HEADER #define GEN6_WRITE_HEADER \ - struct intel_uncore *uncore = &dev_priv->uncore; \ u32 offset = i915_mmio_reg_offset(reg); \ unsigned long irqflags; \ trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ @@ -1262,7 +1258,7 @@ __gen2_write(32) #define __gen6_write(x) \ static void \ -gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ +gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ GEN6_WRITE_HEADER; \ if (NEEDS_FORCE_WAKE(offset)) \ __gen6_gt_wait_for_fifo(uncore); \ @@ -1272,7 +1268,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool #define __gen_write(func, x) \ static void \ -func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ +func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ enum forcewake_domains fw_engine; \ GEN6_WRITE_HEADER; \ fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \ |