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| author | Imre Deak <imre.deak@intel.com> | 2017-07-06 17:40:32 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-27 09:38:52 +0200 |
| commit | 00742cabcc7a4f6bae03cef538c9bb020875115a (patch) | |
| tree | d4b7f459c9706e8a88dcec7e364fc409c8ee201c /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | 9137726abc3bc3217dd3adde67c1dce9a1a87c3f (diff) | |
| download | linux-00742cabcc7a4f6bae03cef538c9bb020875115a.tar.bz2 | |
drm/i915/hsw, bdw: Remove redundant state check during power well toggling
Similarly to the GEN9 power well toggling, saving an occasional extra
MMIO write is not worth the code complexity, let's simplify things.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-11-git-send-email-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 36 |
1 files changed, 13 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 763730febfde..29988d8c0cf6 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -399,36 +399,26 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, static void hsw_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - bool is_enabled, enable_requested; uint32_t tmp; tmp = I915_READ(HSW_PWR_WELL_DRIVER); - is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; - enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; if (enable) { - if (!enable_requested) - I915_WRITE(HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_ENABLE_REQUEST); - - if (!is_enabled) { - DRM_DEBUG_KMS("Enabling power well\n"); - if (intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_STATE_ENABLED, - HSW_PWR_WELL_STATE_ENABLED, - 20)) - DRM_ERROR("Timeout enabling power well\n"); - hsw_power_well_post_enable(dev_priv); - } + I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE_REQUEST); + DRM_DEBUG_KMS("Enabling power well\n"); + if (intel_wait_for_register(dev_priv, + HSW_PWR_WELL_DRIVER, + HSW_PWR_WELL_STATE_ENABLED, + HSW_PWR_WELL_STATE_ENABLED, + 20)) + DRM_ERROR("Timeout enabling power well\n"); + hsw_power_well_post_enable(dev_priv); } else { - if (enable_requested) { - hsw_power_well_pre_disable(dev_priv); - I915_WRITE(HSW_PWR_WELL_DRIVER, 0); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Requesting to disable the power well\n"); - } + hsw_power_well_pre_disable(dev_priv); + I915_WRITE(HSW_PWR_WELL_DRIVER, 0); + POSTING_READ(HSW_PWR_WELL_DRIVER); + DRM_DEBUG_KMS("Requesting to disable the power well\n"); } } |