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| author | Manasi Navare <manasi.d.navare@intel.com> | 2018-08-23 18:48:07 -0700 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2018-08-28 15:11:31 -0700 |
| commit | 5df52391ddbed869c7d67b00fbb013bd64334115 (patch) | |
| tree | 01be988695af07b90e9927f460b178e0d9f3148a /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | b45649fbd5bf94199a84bdeb4515bca926f698a9 (diff) | |
| download | linux-5df52391ddbed869c7d67b00fbb013bd64334115.tar.bz2 | |
drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
This patch fixes the PPS4 and PPS5 register definition macros that were
resulting into an incorect MMIO address.
Fixes: 2efbb2f099fb ("i915/dp/dsc: Add DSC PPS register definitions")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180824014807.14681-1-manasi.d.navare@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
0 files changed, 0 insertions, 0 deletions