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| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2018-07-17 14:11:01 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-07-18 17:47:53 -0700 |
| commit | c7d2959f032ddb0cb3528df4cc08b6b78acb9a09 (patch) | |
| tree | d4bca2620cdbe9e6743a1e120ab1eca66fd486e3 /drivers/gpu/drm/i915/intel_guc_submission.c | |
| parent | dbda5111e2d85ff67452e9f8b82fc9eee73a224c (diff) | |
| download | linux-c7d2959f032ddb0cb3528df4cc08b6b78acb9a09.tar.bz2 | |
i915/dp/dsc: Add Rate Control Range Parameter Registers
RC model has these parameters that correspond with each of
15 ranges of RC buffer threshold value in the RC model.
The three elements are range_min_qp, range_max_qp and
range_bpg_offset.
Add the Rate Control range values for eDP/MIPI and DP case.
The actual values are calculated usung a helper function.
This patch adds the shifts to registers where the value will
be written during atomic commit.
v2:
- Use _MMIO_PIPE() instead of _MMIO(_PICK()) (Manasi)
- Combine shifts (Manasi)
Cc: Jose Souza <jose.souza@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-4-git-send-email-anusha.srivatsa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_submission.c')
0 files changed, 0 insertions, 0 deletions