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authorChris Wilson <chris@chris-wilson.co.uk>2016-08-19 16:54:25 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2016-08-19 17:13:29 +0100
commit8678fdaf396c3aa3732b3d98ce2241633dbc26ba (patch)
tree9f61992a6f0f98671f2c91197a57149d10c974a3 /drivers/gpu/drm/i915/intel_fbc.c
parent12ecf4b979ec79b72e7aff35b172cada85e128a5 (diff)
downloadlinux-8678fdaf396c3aa3732b3d98ce2241633dbc26ba.tar.bz2
drm/i915/fbc: Allow on unfenced surfaces, for recent gen
Only fbc1 is tied to using a fence. Later iterations of fbc are more flexible and allow operation on unfenced frontbuffers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20160819155428.1670-3-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_fbc.c')
-rw-r--r--drivers/gpu/drm/i915/intel_fbc.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index faa67624e1ed..bf8b22ad9aed 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -799,8 +799,10 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
*/
if (cache->fb.tiling_mode != I915_TILING_X ||
cache->fb.fence_reg == I915_FENCE_REG_NONE) {
- fbc->no_fbc_reason = "framebuffer not tiled or fenced";
- return false;
+ if (INTEL_GEN(dev_priv) < 5) {
+ fbc->no_fbc_reason = "framebuffer not tiled or fenced";
+ return false;
+ }
}
if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
cache->plane.rotation != DRM_ROTATE_0) {