diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-11-14 15:42:23 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-11-16 09:44:48 -0800 |
| commit | 063c886197f677f79f37fa62ce77b9df9bb0c3cf (patch) | |
| tree | 422903ae7e6637e989bdc809289b57b249c41125 /drivers/gpu/drm/i915/intel_dpll_mgr.c | |
| parent | 5eca81de88927f3e43fdd6e90e8fa5204be996b7 (diff) | |
| download | linux-063c886197f677f79f37fa62ce77b9df9bb0c3cf.tar.bz2 | |
drm/i915/cnl: Fix wrpll math for higher freqs.
Spec describe all values in MHz. We handle our
clocks in KHz. This includes the best_dco_centrality that was
forgot in the same unity as spec. Consequently we couldn't
get a good divider for high frequenies. Hence HDMI 2.0 wasn't
working.
Spec tells 999999 for initial best_dco_centrality meaning the
max value in MHz.
Since we convert dco from MHz to KHz we also need to convert
this initial best_doc_centrality to 999999000 or 999999999
or even better, to the max that its variable allow.
This patch also replaces the use of "* KHz(1)" with the values
directly on KHz to avoid future confusion.
v2: Use U32_MAX instead of random 99999 as spec tells. (Ville).
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171114234223.10600-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpll_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index fba969cbda37..6cc12abdd39e 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock, struct skl_wrpll_params *wrpll_params) { u32 afe_clock = clock * 5; - u32 dco_min = 7998 * KHz(1); - u32 dco_max = 10000 * KHz(1); + u32 dco_min = 7998000; + u32 dco_max = 10000000; u32 dco_mid = (dco_min + dco_max) / 2; static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 24, 28, 30, 32, 36, 40, @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock, 84, 88, 90, 92, 96, 98, 100, 102, 3, 5, 7, 9, 15, 21 }; u32 dco, best_dco = 0, dco_centrality = 0; - u32 best_dco_centrality = 999999; + u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */ int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0; for (d = 0; d < ARRAY_SIZE(dividers); d++) { |