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author | Animesh Manna <animesh.manna@intel.com> | 2015-08-04 22:02:41 +0530 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-23 09:39:08 +0200 |
commit | 18c237c0f9fa2e1c66e1eb4c305aeff4f28f89bf (patch) | |
tree | 8f22e0e0d59a4bc568c7c4add333290ce8f8768b /drivers/gpu/drm/i915/intel_csr.c | |
parent | adda50b8b32bd559906d82fa32caeaf6c9306f59 (diff) | |
download | linux-18c237c0f9fa2e1c66e1eb4c305aeff4f28f89bf.tar.bz2 |
drm/i915/bxt: Path added of dmc firmware ver1 for BXT.
Broxton also has dmc to manage low-power display engine state.
Path of the firmware added in intel_csr.c.
Naming convention followed as <platform>_dmc_<api-version>.bin
v1: Initial version.
v2: Commit description added based on review comment from Sunil.
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_csr.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_csr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 765dfcd15727..6d1aaff164af 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -42,8 +42,10 @@ */ #define I915_CSR_SKL "i915/skl_dmc_ver1.bin" +#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin" MODULE_FIRMWARE(I915_CSR_SKL); +MODULE_FIRMWARE(I915_CSR_BXT); /* * SKL CSR registers for DC5 and DC6 @@ -409,6 +411,8 @@ void intel_csr_ucode_init(struct drm_device *dev) if (IS_SKYLAKE(dev)) csr->fw_path = I915_CSR_SKL; + else if (IS_BROXTON(dev_priv)) + csr->fw_path = I915_CSR_BXT; else { DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); intel_csr_load_status_set(dev_priv, FW_FAILED); |