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author | Imre Deak <imre.deak@intel.com> | 2016-08-10 14:07:33 +0300 |
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committer | Imre Deak <imre.deak@intel.com> | 2016-08-10 16:01:42 +0300 |
commit | 8090ba8c216ff75c32ecb85c41adf3c5126d8a92 (patch) | |
tree | c85c1d4583d1d748f497bbed212fff9a09443c46 /drivers/gpu/drm/i915/i915_suspend.c | |
parent | 335f752ba948f30e8ebbf3c4217e1714a885be44 (diff) | |
download | linux-8090ba8c216ff75c32ecb85c41adf3c5126d8a92.tar.bz2 |
drm/i915: Apply the PPS register unlock workaround more consistently
Atm, we apply this workaround somewhat inconsistently at the following
points: driver loading, LVDS init, eDP PPS init, system resume. As this
workaround also affects registers other than PPS (timing, PLL) a more
consistent way is to apply it early after the PPS HW context is known to
be lost: driver loading, system resume and on VLV/CHV/BXT when turning
on power domains.
This is needed by the next patch that removes saving/restoring of the
PP_CONTROL register.
This also removes the incorrect programming of the workaround on HSW+
PCH platforms which don't have the register locking mechanism.
v2: (Ville)
- Don't apply the workaround on BXT.
- Simplify platform checks using HAS_DDI().
v3:
- Move the call of intel_pps_unlock_regs_wa() to the more
logical vlv_display_power_well_init() (also fixing CHV) (Ville).
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470827254-21954-5-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
0 files changed, 0 insertions, 0 deletions