diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2020-02-27 14:00:51 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-03-02 12:00:39 -0800 |
| commit | ec1e12645ff3987f660ef9dc21c9db548b43ee9b (patch) | |
| tree | b7adb6d88d2693d1e9702333610e1686d5333176 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | ccc495fd7ac3815702378712bccc1cbfc7852b58 (diff) | |
| download | linux-ec1e12645ff3987f660ef9dc21c9db548b43ee9b.tar.bz2 | |
drm/i915/tgl: Implement Wa_1409804808
This workaround the CS not done issue on PIPE_CONTROL.
v2:
- replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits
- shortened the name of the new bit
BSpec: 52890
BSpec: 46218
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 72de9591f77f..acace016d46c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9140,8 +9140,9 @@ enum { #define THROTTLE_12_5 (7 << 2) #define DISABLE_EARLY_EOT (1 << 1) -#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) -#define GEN12_DISABLE_EARLY_READ BIT(14) +#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) +#define GEN12_DISABLE_EARLY_READ REG_BIT(14) +#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) #define DOP_CLOCK_GATING_DISABLE (1 << 0) |