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| author | Clinton A Taylor <clinton.a.taylor@intel.com> | 2019-09-26 14:06:57 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-09-27 10:40:18 -0700 |
| commit | 978c3e539be210268b6c6cfeef0c97e18c00d7a7 (patch) | |
| tree | c7068f3d48d8adf0193984cb438a6547cff9ca71 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 3b51be4e4061bd5e0f1b73f56cfecaa879c76d51 (diff) | |
| download | linux-978c3e539be210268b6c6cfeef0c97e18c00d7a7.tar.bz2 | |
drm/i915/tgl: Add dkl phy programming sequences
Added DKL Phy sequences and helpers functions to program voltage
swing, clock gating and dp mode.
It is not written in DP enabling sequence but "PHY Clockgating
programming" states that clock gating should be enabled after the
link training but doing so causes all the following trainings to fail
so not enabling it for.
v2:
Setting the right HIP_INDEX_REG bits (José)
v3:
Adding the meaning of each column of tgl_dkl_phy_ddi_translations
Adding if gen >= 12 on intel_ddi_hdmi_level() and
intel_ddi_pre_enable_hdmi() instead of reuse part of gen >= 11 if
v4:
Moved the DP_MODE lane programing to another patch as ICL also
needed it
Sharing icl_phy_set_clock_gating() and icl_program_mg_dp_mode() with
TGL as bits and programing as now it almost identical to ICL
BSpec: 49292
BSpec: 49190
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190926210659.56317-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 014fa5dbde83..058aa5ca8b73 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10249,14 +10249,6 @@ enum skl_power_gate { _DKL_TX_DW18) #define _DKL_DP_MODE 0xA0 -#define DKL_DP_MODE_CFG_GAONPWR_GATING (1 << 1) -#define DKL_DP_MODE_CFG_DIGPWR_GATING (1 << 2) -#define DKL_DP_MODE_CFG_CLNPWR_GATING (1 << 3) -#define DKL_DP_MODE_CFG_TRPWR_GATING (1 << 4) -#define DKL_DP_MODE_CFG_TR2PWR_GATING (1 << 5) -#define DKL_DP_MODE_CFG_GATING_CTRL_MASK (0x1f << 1) -#define DKL_DP_MODE_CFG_DP_X1_MODE (1 << 6) -#define DKL_DP_MODE_CFG_DP_X2_MODE (1 << 7) #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ _DKL_PHY1_BASE, \ _DKL_PHY2_BASE) + \ |