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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2016-06-07 17:19:09 +0300 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-06-08 16:25:10 +0300 |
| commit | 44fff99ff25f1dd528b260dc3f03f2a38c6155a7 (patch) | |
| tree | bea35b581ea7170261fc65f428a2017972c8b7d1 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 6fc29133eafb9eb3338024884f3a5a4fa844d45c (diff) | |
| download | linux-44fff99ff25f1dd528b260dc3f03f2a38c6155a7.tar.bz2 | |
drm/i915/skl: Add WAC6entrylatency
This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.
v2: rebase
References: HSD#4712857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-18-git-send-email-mika.kuoppala@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 11e10a0ccd37..e8cf7a93f33f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2167,6 +2167,9 @@ enum skl_disp_power_wells { #define FBC_LL_SIZE (1536) +#define FBC_LLC_READ_CTRL _MMIO(0x9044) +#define FBC_LLC_FULLY_OPEN (1<<30) + /* Framebuffer compression for GM45+ */ #define DPFC_CB_BASE _MMIO(0x3200) #define DPFC_CONTROL _MMIO(0x3208) |