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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2016-10-21 13:55:46 -0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2016-10-24 17:39:03 -0200 |
| commit | 0fc6a9dc94e44c8eaca364b9da03d26862d6b068 (patch) | |
| tree | ac0fbfc4a46a676ccf2697788fd68c3f72972217 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 79f2624b1b9f776b173b41d743fb3dd7374b3827 (diff) | |
| download | linux-0fc6a9dc94e44c8eaca364b9da03d26862d6b068.tar.bz2 | |
drm/i915/fbc: fix FBC_COMPRESSION_MASK on BDW+
Its size is 11:0 instead of 10:0. Found by inspecting the spec. I'm
not aware of any real-world IGT failures caused by this.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1477065346-13736-2-git-send-email-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 00efaa13974d..a9be3f037f43 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2188,8 +2188,9 @@ enum skl_disp_power_wells { #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) -#define FBC_STATUS2 _MMIO(0x43214) -#define FBC_COMPRESSION_MASK 0x7ff +#define FBC_STATUS2 _MMIO(0x43214) +#define IVB_FBC_COMPRESSION_MASK 0x7ff +#define BDW_FBC_COMPRESSION_MASK 0xfff #define FBC_LL_SIZE (1536) |