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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2020-05-10 11:24:31 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-05-11 17:26:38 +0100 |
| commit | 1c8ee8b92fb6ac9d5975147cc902e8c142eca338 (patch) | |
| tree | 76515efc078545477d76baff954511f425041c81 /drivers/gpu/drm/i915/i915_pci.c | |
| parent | 84eac0c65940d9633247b0c8c826d4bcb7307351 (diff) | |
| download | linux-1c8ee8b92fb6ac9d5975147cc902e8c142eca338.tar.bz2 | |
drm/i915/gt: Restore Cherryview back to full-ppgtt
This reverts commit 0b718ba1e884f64dce27c19311dd2859b87e56b9.
There are still some residual issues with asynchronous binding and
execution, but since commit 92581f9fb99c ("drm/i915: Immediately execute
the fenced work") we prefer not to use asynchronous binds, and the
remaining issues do not seem restricted to Cherryview [at least the ones
seen over a few dozen CI runs, less frequent issues are sure to be
discovered!]
These issues seem to be mitigated, if not eliminated entirely, by the
previous commit 84eac0c65940 ("drm/i915/gt: Force pte cacheline to main
memory").
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200510102431.21959-3-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 2fc25ec12c3d..193048ce3c3a 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -615,7 +615,7 @@ static const struct intel_device_info chv_info = { .has_logical_ring_contexts = 1, .display.has_gmch = 1, .dma_mask_size = 39, - .ppgtt_type = INTEL_PPGTT_ALIASING, + .ppgtt_type = INTEL_PPGTT_FULL, .ppgtt_size = 32, .has_reset_engine = 1, .has_snoop = true, |