diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-09-08 17:02:10 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-09-14 16:20:57 +0300 |
| commit | 8dec2fc11b8cdad7d2b5679ebf0b742d511eacae (patch) | |
| tree | fddfce4d92e9ff861cd9931990dfdaf39b42ef0c /drivers/gpu/drm/i915/i915_drv.h | |
| parent | b41e58ffe49172eb260e95c217d3e1f0f7432ba6 (diff) | |
| download | linux-8dec2fc11b8cdad7d2b5679ebf0b742d511eacae.tar.bz2 | |
drm/i915: Nuke CACHE_MODE_0 save/restore
The CACHE_MODE_0 save/restore was added without explanation in
commit 1f84e550a870 ("drm/i915 more registers for S3 (DSPCLK_GATE_D,
CACHE_MODE_0, MI_ARB_STATE)"). If there are any bits we care about
those should be set explicitly during some appropriate init function.
Let's assume it's all good and just nuke this magic save/restore.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200908140210.31048-4-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3b5166bb8b26..151f11f14b06 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -537,7 +537,6 @@ struct intel_gmbus { struct i915_suspend_saved_registers { u32 saveDSPARB; - u32 saveCACHE_MODE_0; u32 saveSWF0[16]; u32 saveSWF1[16]; u32 saveSWF3[3]; |