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authorYuanhan Liu <yuanhan.liu@linux.intel.com>2010-12-15 15:42:32 +0800
committerChris Wilson <chris@chris-wilson.co.uk>2010-12-15 11:22:27 +0000
commit9c04f015ebc2cc2cca5a4a576deb82a311578edc (patch)
tree9c4b04dc9a07c943c431ce60d45113a1cd78d442 /drivers/gpu/drm/i915/i915_dma.c
parent1398261a2e84c537c409259cfe9db3d0abcd9f99 (diff)
downloadlinux-9c04f015ebc2cc2cca5a4a576deb82a311578edc.tar.bz2
drm/i915: Add frame buffer compression on Sandybridge
Add frame buffer compression on Sandybridge. The method is similar to Ironlake, except that two new registers of type GTTMMADR must be written with the right fence info. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e9fb8953c606..3f7b20392e26 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1078,7 +1078,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
if (!cfb_base)
goto err_fb;
- if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
+ if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
4096, 4096, 0);
if (compressed_llb)
@@ -1096,7 +1096,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
intel_disable_fbc(dev);
dev_priv->compressed_fb = compressed_fb;
- if (IS_IRONLAKE_M(dev))
+ if (HAS_PCH_SPLIT(dev))
I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
else if (IS_GM45(dev)) {
I915_WRITE(DPFC_CB_BASE, compressed_fb->start);