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| author | Zhao Yan <yan.y.zhao@intel.com> | 2018-05-08 14:52:30 +0800 |
|---|---|---|
| committer | Zhi Wang <zhi.a.wang@intel.com> | 2018-05-14 05:18:55 +0800 |
| commit | 3d8b9e258b9dbbeb0cdeb1cf5885e40d63d564ab (patch) | |
| tree | 8732fb8a0f038988c8896ae9bbb7ee2e158cdb72 /drivers/gpu/drm/i915/gvt/cmd_parser.c | |
| parent | b99f514f5dfa38e04ef0b628d82a97772945cae7 (diff) | |
| download | linux-3d8b9e258b9dbbeb0cdeb1cf5885e40d63d564ab.tar.bz2 | |
drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registers
Each ring has a NOPID register and currently they are regarded as default
value of force_to_nonpriv registers in guest drivers
Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/cmd_parser.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 9ec2cd982705..737cc824344d 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -817,8 +817,15 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, { struct intel_gvt *gvt = s->vgpu->gvt; unsigned int data = cmd_val(s, index + 1); + u32 ring_base; + u32 nopid; + struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; + + ring_base = dev_priv->engine[s->ring_id]->mmio_base; + nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); - if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) { + if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) && + data != nopid) { gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n", offset, data); return -EPERM; |