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| author | Michel Thierry <michel.thierry@intel.com> | 2019-09-06 15:23:14 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-09-06 18:12:58 +0100 |
| commit | 5bf05dc58d65b215437df3013163a7eea78d5d4c (patch) | |
| tree | d8288d0a4d72955da2185550a10854025b86112c /drivers/gpu/drm/i915/gem/i915_gem_pm.c | |
| parent | cdb736fa8b8b65740030ba8f9dc87f0fc3313858 (diff) | |
| download | linux-5bf05dc58d65b215437df3013163a7eea78d5d4c.tar.bz2 | |
drm/i915/tgl: Register state context definition for Gen12
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the registers that
are contiguous in functions we can reuse.
v2: alias, virtual engine, rpcs, prune unused regs
v3: use engine base (Daniele), take ctx_bb for all
Bspec: 46255
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Tested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
[ickle: Tweaked the GEM_WARN_ON after settling on a compromise with
Daniele]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190906122314.2146-2-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gem/i915_gem_pm.c')
0 files changed, 0 insertions, 0 deletions