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authorChris Wilson <chris@chris-wilson.co.uk>2015-06-10 15:58:01 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-06-19 17:25:17 +0200
commitafcd950cafea6e27b739fe7772cbbeed37d05b8b (patch)
tree523aeecbb69c5e5455b8f999dd76527b1e1d6b01 /drivers/gpu/drm/drm_cache.c
parent2465ff6217f1b63e194cfd57018fa42abe7fcdf0 (diff)
downloadlinux-afcd950cafea6e27b739fe7772cbbeed37d05b8b.tar.bz2
drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
As the clflush operates on cache lines, and we can flush any byte address, in order to flush all bytes given in the range we issue an extra clflush on the last byte to ensure the last cacheline is flushed. We can can the iteration to be over the actual cache lines to avoid this double clflush on the last byte. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/drm_cache.c')
-rw-r--r--drivers/gpu/drm/drm_cache.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 9a62d7a53553..6743ff7dccfa 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -130,11 +130,12 @@ drm_clflush_virt_range(void *addr, unsigned long length)
{
#if defined(CONFIG_X86)
if (cpu_has_clflush) {
+ const int size = boot_cpu_data.x86_clflush_size;
void *end = addr + length;
+ addr = (void *)(((unsigned long)addr) & -size);
mb();
- for (; addr < end; addr += boot_cpu_data.x86_clflush_size)
+ for (; addr < end; addr += size)
clflushopt(addr);
- clflushopt(end - 1);
mb();
return;
}