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author | Hawking Zhang <Hawking.Zhang@amd.com> | 2019-11-04 16:20:06 +0800 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2019-11-06 16:27:47 -0500 |
commit | 58f46d4b65021083ef4b4d49c6e2c58e5783f626 (patch) | |
tree | 1bb6e064883013b7ef981c18e54dc9768cbcab6d /drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | |
parent | d7c5782acd354bdb5ed0fa10e1e397eaed558390 (diff) | |
download | linux-58f46d4b65021083ef4b4d49c6e2c58e5783f626.tar.bz2 |
drm/amdgpu: disallow direct upload save restore list from gfx driver
Direct uploading save/restore list via mmio register writes breaks the security
policy. Instead, the driver should pass s&r list to psp.
For all the ASICs that use rlc v2_1 headers, the driver actually upload s&r list
twice, in non-psp ucode front door loading phase and gfx pg initialization phase.
The latter is not allowed.
VG12 is the only exception where the driver still keeps legacy approach for S&R
list uploading. In theory, this can be elimnated if we have valid srcntl ucode
for VG12.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Candice Li <Candice.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h')
0 files changed, 0 insertions, 0 deletions