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| author | Huang Rui <ray.huang@amd.com> | 2019-03-24 19:22:07 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:26 -0500 |
| commit | 0de94acf90e3ac61a11782cbb2394799bba4c96d (patch) | |
| tree | 4423403dbac6b5d13b0fdeea1b8868d2cbd460bf /drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | |
| parent | 54b998ca8d1ccbf626b398ff6ad0d1dfa771e197 (diff) | |
| download | linux-0de94acf90e3ac61a11782cbb2394799bba4c96d.tar.bz2 | |
drm/amd/powerplay: introduce smu clk type to handle ppclk for each asic
This patch introduces new smu clk type, it's to handle the different ppclk
defines for each asic with the same smu ip.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h index cd5e66b82ce1..cae6619d2df5 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h @@ -40,6 +40,9 @@ #define TEMP_RANGE_MIN (0) #define TEMP_RANGE_MAX (80 * 1000) +#define CLK_MAP(clk, index) \ + [SMU_##clk] = index + struct smu_11_0_max_sustainable_clocks { uint32_t display_clock; uint32_t phy_clock; |