diff options
| author | Kenneth Feng <kenneth.feng@amd.com> | 2019-10-16 16:20:38 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-17 16:24:15 -0400 |
| commit | 5441dd0e2caadc6038a8c1ccd16cf3c9cdb62db1 (patch) | |
| tree | da7a988d5e005b7e9f7dbe96cadf65cdcfc5a465 /drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | |
| parent | f839110157aed1396506dfab715f523344ab9724 (diff) | |
| download | linux-5441dd0e2caadc6038a8c1ccd16cf3c9cdb62db1.tar.bz2 | |
drm/amd/powerplay: bug fix for memory clock request from display
In some cases, display fixes memory clock frequency to a high value
rather than the natural memory clock switching.
When we comes back from s3 resume, the request from display is not reset,
this causes the bug which makes the memory clock goes into a low value.
Then due to the insuffcient memory clock, the screen flicks.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/amdgpu_smu.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index e2a03f411d6b..ee374df32b19 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -1354,6 +1354,8 @@ static int smu_resume(void *handle) if (smu->is_apu) smu_set_gfx_cgpg(&adev->smu, true); + smu->disable_uclk_switch = 0; + mutex_unlock(&smu->mutex); pr_info("SMU is resumed successfully!\n"); |