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| author | Dave Airlie <airlied@redhat.com> | 2017-11-16 12:39:40 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2017-11-16 12:39:40 +1000 |
| commit | 49e37ba07a3ae697086c0a1a32c113a1f177d138 (patch) | |
| tree | 492fc0db4fc5d7b417cb9e6a39580bce0ccbc33a /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |
| parent | 4479ed411cf41b42b1c548f73099287fff2330ff (diff) | |
| parent | 00f713c6dc657397ba37b42d7f6887f526c730c6 (diff) | |
| download | linux-49e37ba07a3ae697086c0a1a32c113a1f177d138.tar.bz2 | |
Merge branch 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux into drm-next
Various fixes for DC for 4.15.
* 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux:
drm/amd/display: fix MST link training fail division by 0
drm/amd/display: Fix formatting for null pointer dereference fix
drm/amd/display: Remove dangling planes on dc commit state
drm/amd/display: add flip_immediate to commit update for stream
drm/amd/display: Miss register MST encoder cbs
drm/amd/display: Fix warnings on S3 resume
drm/amd/display: use num_timing_generator instead of pipe_count
drm/amd/display: use configurable FBC option in dm
drm/amd/display: fix AZ clock not enabled before program AZ endpoint
amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 63c2f5266142..961ad5c3b454 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -202,7 +202,7 @@ static void dcn10_log_hw_state(struct dc *dc) DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t " "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n"); - for (i = 0; i < pool->pipe_count; i++) { + for (i = 0; i < pool->res_cap->num_timing_generator; i++) { struct timing_generator *tg = pool->timing_generators[i]; struct dcn_otg_state s = {0}; |