diff options
| author | Tony Cheng <tony.cheng@amd.com> | 2017-02-28 22:52:29 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:17:56 -0400 |
| commit | 773d1bcae744379a03f525bfc9249d8abf0550a8 (patch) | |
| tree | c3778b17030dd169bab1697009e05b02005b4b1f /drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | |
| parent | d98e5cc2ddacb34e9cdf1c06dce2758198af0120 (diff) | |
| download | linux-773d1bcae744379a03f525bfc9249d8abf0550a8.tar.bz2 | |
drm/amd/display: remove independent lock as we have no use case today
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index 89a8274e12ea..17cdd70a2c27 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -46,7 +46,6 @@ void dce_enable_fe_clock(struct dce_hwseq *hws, void dce_pipe_control_lock(struct core_dc *dc, struct pipe_ctx *pipe, - enum pipe_lock_control control_mask, bool lock) { uint32_t lock_val = lock ? 1 : 0; @@ -59,18 +58,10 @@ void dce_pipe_control_lock(struct core_dc *dc, BLND_BLND_V_UPDATE_LOCK, &blnd, BLND_V_UPDATE_LOCK_MODE, &update_lock_mode); - if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS) - dcp_grph = lock_val; - - if (control_mask & PIPE_LOCK_CONTROL_SCL) - scl = lock_val; - - if (control_mask & PIPE_LOCK_CONTROL_BLENDER) - blnd = lock_val; - - if (control_mask & PIPE_LOCK_CONTROL_MODE) - update_lock_mode = lock_val; - + dcp_grph = lock_val; + scl = lock_val; + blnd = lock_val; + update_lock_mode = lock_val; REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val, BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph, @@ -82,7 +73,7 @@ void dce_pipe_control_lock(struct core_dc *dc, BLND_V_UPDATE_LOCK_MODE, update_lock_mode); if (hws->wa.blnd_crtc_trigger) { - if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) { + if (!lock) { uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]); REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value); } |