diff options
| author | AMD\ktsao <kenny.tsao@amd.com> | 2017-07-30 14:18:36 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:16:02 -0400 |
| commit | 43193c7991de7a2112fe2ddcfd930733bc357862 (patch) | |
| tree | 89fff4e59c12925e33a044f0b8905945f457098d /drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | |
| parent | 7a09f5be98df25a7253e4647e801120b37b90feb (diff) | |
| download | linux-43193c7991de7a2112fe2ddcfd930733bc357862.tar.bz2 | |
drm/amd/display: remove DCN1 guard as DCN1 is already open sourced.
Signed-off-by: Kenny Tsao <kenny.tsao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_abm.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 91 |
1 files changed, 43 insertions, 48 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index e0abd2d49370..59e909ec88f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -54,21 +54,19 @@ SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ SR(BIOS_SCRATCH_2) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #define ABM_DCN10_REG_LIST(id)\ - ABM_COMMON_REG_LIST_DCE_BASE(), \ - SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ - SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ - SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ - SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ - SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ - SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ - SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ - SRI(BL1_PWM_USER_LEVEL, ABM, id), \ - SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ - SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ - NBIO_SR(BIOS_SCRATCH_2) -#endif +#define ABM_DCN10_REG_LIST(id)\ + ABM_COMMON_REG_LIST_DCE_BASE(), \ + SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ + SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ + SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ + SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_USER_LEVEL, ABM, id), \ + SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ + SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ + NBIO_SR(BIOS_SCRATCH_2) #define ABM_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -120,39 +118,36 @@ ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) - -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ - ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ - ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ - ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ - ABM1_HG_VMAX_SEL, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ - ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ - ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ - ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ - ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ - ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ - BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ - ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ - BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ - ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ - BL1_PWM_USER_LEVEL, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ - ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ - ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ - ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ - ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ - ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ - ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) -#endif +#define ABM_MASK_SH_LIST_DCN10(mask_sh) \ + ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_VMAX_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ + BL1_PWM_USER_LEVEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ |