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| author | Tao Zhou <tao.zhou1@amd.com> | 2019-07-29 17:01:39 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-02 10:30:38 -0500 |
| commit | b7f92097f5bc5129cb386340ec54e6f40639d6e3 (patch) | |
| tree | 2847356571947341aae30fd7f81154ab94be4a1d /drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | |
| parent | 51437623a0a14a5af74aee144a0f2d5790ab1420 (diff) | |
| download | linux-b7f92097f5bc5129cb386340ec54e6f40639d6e3.tar.bz2 | |
drm/amdgpu: implement umc ras init function
enable umc ce interrupt and initialize ecc error count
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/umc_v6_1.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h index ad4598c0e495..dab9cbd292c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h @@ -37,6 +37,13 @@ /* UMC regiser per channel offset */ #define UMC_V6_1_PER_CHANNEL_OFFSET 0x800 +/* EccErrCnt max value */ +#define UMC_V6_1_CE_CNT_MAX 0xffff +/* umc ce interrupt threshold */ +#define UMC_V6_1_CE_INT_THRESHOLD 0xffff +/* umc ce count initial value */ +#define UMC_V6_1_CE_CNT_INIT (UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD) + extern const struct amdgpu_umc_funcs umc_v6_1_funcs; extern const uint32_t umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM]; |