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authorKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>2017-06-05 12:08:03 -0700
committerLee Jones <lee.jones@linaro.org>2017-06-19 15:44:44 +0100
commita1d28c5991137f789162f412764dd7471aca6ec0 (patch)
treebe3c78eec92d02eb253b581e95010327dc229f91 /drivers/gpio
parentc4949630fe437bc15346abbd1a92dee8e80a85d4 (diff)
downloadlinux-a1d28c5991137f789162f412764dd7471aca6ec0.tar.bz2
mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
Currently all PMIC GPIO domain IRQs are consumed by the same device(bxt_wcove_gpio), so there is no need to export them as separate interrupts. We can just export only the first level GPIO IRQ(BXTWC_GPIO_LVL1_IRQ) as an IRQ resource and let the GPIO device driver(bxt_wcove_gpio) handle the GPIO sub domain IRQs based on status value of GPIO level2 interrupt status register. Also, just using only the first level IRQ will eliminate the bug involved in requesting only the second level IRQ and not explicitly enable the first level IRQ. For more info on this issue please read the details at, https://lkml.org/lkml/2017/2/27/148 This patch also makes relevant change in Whiskey cove GPIO driver to use only first level PMIC GPIO IRQ. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-wcove.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
index 7b1bc20be209..bba7704e1654 100644
--- a/drivers/gpio/gpio-wcove.c
+++ b/drivers/gpio/gpio-wcove.c
@@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
if (!wg)
return -ENOMEM;
- wg->regmap_irq_chip = pmic->irq_chip_data_level2;
+ wg->regmap_irq_chip = pmic->irq_chip_data;
platform_set_drvdata(pdev, wg);
@@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
+ /* Enable GPIO0 interrupts */
+ ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
+ 0x00);
+ if (ret)
+ return ret;
+
+ /* Enable GPIO1 interrupts */
+ ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
+ 0x00);
+ if (ret)
+ return ret;
+
return 0;
}