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| author | Kumar Gala <galak@codeaurora.org> | 2015-03-11 16:28:10 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@codeaurora.org> | 2015-04-28 14:20:40 -0500 |
| commit | b6a1dfbc7d57409accf213e78db7b059c206be9e (patch) | |
| tree | dddf2ba29a86607a3c7712ce1288552a71d58f9c /drivers/firmware/qcom_scm.h | |
| parent | 7ce75bb2c05ef6949ab0b93633e052f46855690d (diff) | |
| download | linux-b6a1dfbc7d57409accf213e78db7b059c206be9e.tar.bz2 | |
firmware: qcom: scm: Split out 32-bit specific SCM code
Split out the 32-bit SCM implementation into its own file to prep for
supporting a 64-bit/ARM64 implementation as well. We create a simple shim
to ensure both versions conform to the same interface.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'drivers/firmware/qcom_scm.h')
| -rw-r--r-- | drivers/firmware/qcom_scm.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h new file mode 100644 index 000000000000..1172be917307 --- /dev/null +++ b/drivers/firmware/qcom_scm.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __QCOM_SCM_INT_H +#define __QCOM_SCM_INT_H + +#define QCOM_SCM_SVC_BOOT 0x1 +#define QCOM_SCM_BOOT_ADDR 0x1 +#define QCOM_SCM_BOOT_ADDR_MC 0x11 + +#define QCOM_SCM_FLAG_HLOS 0x01 +#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02 +#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04 +extern int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus); +extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); + +#define QCOM_SCM_CMD_TERMINATE_PC 0x2 +#define QCOM_SCM_FLUSH_FLAG_MASK 0x3 +#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10 +extern void __qcom_scm_cpu_power_down(u32 flags); + +/* common error codes */ +#define QCOM_SCM_ENOMEM -5 +#define QCOM_SCM_EOPNOTSUPP -4 +#define QCOM_SCM_EINVAL_ADDR -3 +#define QCOM_SCM_EINVAL_ARG -2 +#define QCOM_SCM_ERROR -1 +#define QCOM_SCM_INTERRUPTED 1 + +#endif |