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authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-17 10:54:41 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-17 10:54:41 -0800
commite1288cd72f54e7fc16ae9ebb4d0647537ef848d4 (patch)
treeb4fd87b9307d8041fb680cb9b8fbf787ec968df7 /drivers/dma/intel_mid_dma.c
parente78bf5e6cbe837daa6ab628a5f679548742994d3 (diff)
parent94ae85220a07d357d4937086c490854f63344de4 (diff)
downloadlinux-e1288cd72f54e7fc16ae9ebb4d0647537ef848d4.tar.bz2
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (63 commits) ARM: PL08x: cleanup comments Update CONFIG_MD_RAID6_PQ to CONFIG_RAID6_PQ in drivers/dma/iop-adma.c ARM: PL08x: fix a warning Fix dmaengine_submit() return type dmaengine: at_hdmac: fix race while monitoring channel status dmaengine: at_hdmac: flags located in first descriptor dmaengine: at_hdmac: use subsys_initcall instead of module_init dmaengine: at_hdmac: no need set ACK in new descriptor dmaengine: at_hdmac: trivial add precision to unmapping comment dmaengine: at_hdmac: use dma_address to program DMA hardware pch_dma: support new device ML7213 IOH ARM: PL08x: prevent dma_set_runtime_config() reconfiguring memcpy channels ARM: PL08x: allow dma_set_runtime_config() to return errors ARM: PL08x: fix locking between prepare function and submit function ARM: PL08x: introduce 'phychan_hold' to hold on to physical channels ARM: PL08x: put txd's on the pending list in pl08x_tx_submit() ARM: PL08x: rename 'desc_list' as 'pend_list' ARM: PL08x: implement unmapping of memcpy buffers ARM: PL08x: store prep_* flags in async_tx structure ARM: PL08x: shrink srcbus/dstbus in txd structure ...
Diffstat (limited to 'drivers/dma/intel_mid_dma.c')
-rw-r--r--drivers/dma/intel_mid_dma.c33
1 files changed, 24 insertions, 9 deletions
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 78266382797e..798f46a4590d 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -664,11 +664,20 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
/*calculate CTL_LO*/
ctl_lo.ctl_lo = 0;
ctl_lo.ctlx.int_en = 1;
- ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width;
- ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width;
ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;
ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;
+ /*
+ * Here we need some translation from "enum dma_slave_buswidth"
+ * to the format for our dma controller
+ * standard intel_mid_dmac's format
+ * 1 Byte 0b000
+ * 2 Bytes 0b001
+ * 4 Bytes 0b010
+ */
+ ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width / 2;
+ ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width / 2;
+
if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
ctl_lo.ctlx.tt_fc = 0;
ctl_lo.ctlx.sinc = 0;
@@ -746,8 +755,18 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
BUG_ON(!mids);
if (!midc->dma->pimr_mask) {
- pr_debug("MDMA: SG list is not supported by this controller\n");
- return NULL;
+ /* We can still handle sg list with only one item */
+ if (sg_len == 1) {
+ txd = intel_mid_dma_prep_memcpy(chan,
+ mids->dma_slave.dst_addr,
+ mids->dma_slave.src_addr,
+ sgl->length,
+ flags);
+ return txd;
+ } else {
+ pr_warn("MDMA: SG list is not supported by this controller\n");
+ return NULL;
+ }
}
pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
@@ -758,6 +777,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
pr_err("MDMA: Prep memcpy failed\n");
return NULL;
}
+
desc = to_intel_mid_dma_desc(txd);
desc->dirn = direction;
ctl_lo.ctl_lo = desc->ctl_lo;
@@ -1021,11 +1041,6 @@ static irqreturn_t intel_mid_dma_interrupt(int irq, void *data)
/*DMA Interrupt*/
pr_debug("MDMA:Got an interrupt on irq %d\n", irq);
- if (!mid) {
- pr_err("ERR_MDMA:null pointer mid\n");
- return -EINVAL;
- }
-
pr_debug("MDMA: Status %x, Mask %x\n", tfr_status, mid->intr_mask);
tfr_status &= mid->intr_mask;
if (tfr_status) {