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authorDan Carpenter <dan.carpenter@oracle.com>2015-11-04 16:38:31 +0300
committerVinod Koul <vinod.koul@intel.com>2015-11-16 09:07:35 +0530
commitf5ea7ad252452f0b461e04a0d0e468f1f6ad8b3b (patch)
tree67707c3b0712600e880551df70b1d77c36f39768 /drivers/dma/edma.c
parent638bdc8ce845285e1112f4870aded1638187fc98 (diff)
downloadlinux-f5ea7ad252452f0b461e04a0d0e468f1f6ad8b3b.tar.bz2
dmaengine: edma: predecence bug in GET_NUM_QDMACH()
The current code uses bits 0-2 instead of 4-6 as the comment says. Fixes: 633e42b8c546 ('dmaengine: edma: Get qDMA channel information from HW also') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/edma.c')
-rw-r--r--drivers/dma/edma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index c69d22c0b9ba..0675e268d577 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -107,7 +107,7 @@
/* CCCFG register */
#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
-#define GET_NUM_QDMACH(x) (x & 0x70 >> 4) /* bits 4-6 */
+#define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */