diff options
author | Dan Williams <dan.j.williams@intel.com> | 2022-05-18 16:35:17 -0700 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 08:50:42 -0700 |
commit | fcfbc93cc33ec601f00f113eca6fc484b930532d (patch) | |
tree | 34f9211524cad8a5a060d257612d9126e2bf9c22 /drivers/cxl/core/pci.c | |
parent | 5e5f4ad52f33c125af9b91d4c3b7cad59c13772e (diff) | |
download | linux-fcfbc93cc33ec601f00f113eca6fc484b930532d.tar.bz2 |
cxl/port: Reuse 'struct cxl_hdm' context for hdm init
The port driver maps component registers for port operations. Reuse that
mapping for HDM Decoder Capability setup / enable. Move
devm_cxl_setup_hdm() before cxl_hdm_decode_init() and plumb @cxlhdm
through the hdm init helpers.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291691712.1426646.14336397551571515480.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/core/pci.c')
-rw-r--r-- | drivers/cxl/core/pci.c | 39 |
1 files changed, 10 insertions, 29 deletions
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 7d2238edc379..3305e9b750af 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -176,29 +176,14 @@ static int wait_for_valid(struct cxl_dev_state *cxlds) } static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds, + struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info) { - struct cxl_register_map map; - struct cxl_component_reg_map *cmap = &map.component_map; - bool global_enable, retval = false; - void __iomem *crb; + void __iomem *hdm = cxlhdm->regs.hdm_decoder; + bool global_enable; u32 global_ctrl; - /* map hdm decoder */ - crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE); - if (!crb) { - dev_dbg(cxlds->dev, "Failed to map component registers\n"); - return false; - } - - cxl_probe_component_regs(cxlds->dev, crb, cmap); - if (!cmap->hdm_decoder.valid) { - dev_dbg(cxlds->dev, "Invalid HDM decoder registers\n"); - goto out; - } - - global_ctrl = readl(crb + cmap->hdm_decoder.offset + - CXL_HDM_DECODER_CTRL_OFFSET); + global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE; /* @@ -210,9 +195,7 @@ static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds, * match. */ if (!global_enable && info->mem_enabled && info->ranges) - goto out; - - retval = true; + return false; /* * Permanently (for this boot at least) opt the device into HDM @@ -222,22 +205,20 @@ static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds, if (!global_enable) { dev_dbg(cxlds->dev, "Enabling HDM decode\n"); writel(global_ctrl | CXL_HDM_DECODER_ENABLE, - crb + cmap->hdm_decoder.offset + - CXL_HDM_DECODER_CTRL_OFFSET); + hdm + CXL_HDM_DECODER_CTRL_OFFSET); } -out: - iounmap(crb); - return retval; + return true; } /** * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint * @cxlds: Device state + * @cxlhdm: Mapped HDM decoder Capability * * Try to enable the endpoint's HDM Decoder Capability */ -int cxl_hdm_decode_init(struct cxl_dev_state *cxlds) +int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm) { struct pci_dev *pdev = to_pci_dev(cxlds->dev); struct cxl_endpoint_dvsec_info info = { 0 }; @@ -331,7 +312,7 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds) * If DVSEC ranges are being used instead of HDM decoder registers there * is no use in trying to manage those. */ - if (!__cxl_hdm_decode_init(cxlds, &info)) { + if (!__cxl_hdm_decode_init(cxlds, cxlhdm, &info)) { dev_err(dev, "Legacy range registers configuration prevents HDM operation.\n"); return -EBUSY; |