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| author | Arnd Bergmann <arnd@arndb.de> | 2014-09-25 17:42:57 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2014-09-25 17:42:57 +0200 |
| commit | e36087998a3b01f3c6c93fa9465e40103f427315 (patch) | |
| tree | 029c1db87eb84dc72e796174455f0c453885fa74 /drivers/cpuidle | |
| parent | 3b8f5030ddcf51112542e1e6ef27da237642069d (diff) | |
| parent | 8097171e19bb69f3e2226827440b71ececa5d74f (diff) | |
| download | linux-e36087998a3b01f3c6c93fa9465e40103f427315.tar.bz2 | |
Merge tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx into next/soc
Pull "arm: Xilinx Zynq cleanup patches for v3.18" from Michal Simek:
- PM support
- Fix L2 useless setting
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Remove useless L2C AUX setting
ARM: zynq: Rename 'zynq_platform_cpu_die'
ARM: zynq: Remove hotplug.c
ARM: zynq: Synchronise zynq_cpu_die/kill
ARM: zynq: cpuidle: Remove pointless code
ARM: zynq: Remove invalidate cache for cpu die
ARM: zynq: PM: Enable DDR clock stop
ARM: zynq: DT: Add DDRC node
Documentation: devicetree: Add binding for Synopsys DDR controller
ARM: zynq: PM: Enable A9 internal clock gating feature
Diffstat (limited to 'drivers/cpuidle')
| -rw-r--r-- | drivers/cpuidle/cpuidle-zynq.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/drivers/cpuidle/cpuidle-zynq.c b/drivers/cpuidle/cpuidle-zynq.c index aded75928028..c61b8b2a7c77 100644 --- a/drivers/cpuidle/cpuidle-zynq.c +++ b/drivers/cpuidle/cpuidle-zynq.c @@ -26,7 +26,6 @@ */ #include <linux/init.h> -#include <linux/cpu_pm.h> #include <linux/cpuidle.h> #include <linux/platform_device.h> #include <asm/proc-fns.h> @@ -38,15 +37,9 @@ static int zynq_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - /* Devices must be stopped here */ - cpu_pm_enter(); - /* Add code for DDR self refresh start */ cpu_do_idle(); - /* Add code for DDR self refresh stop */ - cpu_pm_exit(); - return index; } @@ -59,8 +52,7 @@ static struct cpuidle_driver zynq_idle_driver = { .enter = zynq_enter_idle, .exit_latency = 10, .target_residency = 10000, - .flags = CPUIDLE_FLAG_TIME_VALID | - CPUIDLE_FLAG_TIMER_STOP, + .flags = CPUIDLE_FLAG_TIME_VALID, .name = "RAM_SR", .desc = "WFI and RAM Self Refresh", }, |