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| author | Heiner Kallweit <hkallweit1@gmail.com> | 2019-07-31 23:05:10 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-08-02 18:16:04 -0700 |
| commit | aa6b1956158f1afc52761137620d4b3f8a058d24 (patch) | |
| tree | ae2e398a615a9348ca4833f94ac395bae875719c /drivers/clocksource | |
| parent | 2802d2cf24b1ca7ea4c54dde266ded6a16020eb5 (diff) | |
| download | linux-aa6b1956158f1afc52761137620d4b3f8a058d24.tar.bz2 | |
net: phy: fix race in genphy_update_link
In phy_start_aneg() autoneg is started, and immediately after that
link and autoneg status are read. As reported in [0] it can happen that
at time of this read the PHY has reset the "aneg complete" bit but not
yet the "link up" bit, what can result in a false link-up detection.
To fix this don't report link as up if we're in aneg mode and PHY
doesn't signal "aneg complete".
[0] https://marc.info/?t=156413509900003&r=1&w=2
Fixes: 4950c2ba49cc ("net: phy: fix autoneg mismatch case in genphy_read_status")
Reported-by: liuyonglong <liuyonglong@huawei.com>
Tested-by: liuyonglong <liuyonglong@huawei.com>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/clocksource')
0 files changed, 0 insertions, 0 deletions