Merge branch 'clockevents/3.16' of git://git.linaro.org/people/daniel.lezcano/linux into timers/core

This pull request contains the following changes:

* Laurent Pinchart did a lot of modifications to prepare the DT
  support.  These modifications include a lot of cleanup (structure
  renaming, preparation to support multiple channel, kzalloc usage,
  ...) and then finishes to drop the old code to the new one.

* Jingoo Han removed the dev_err when an allocation fails because this
  error is already given by the mm subsystems.

* Matthew Leach added the ARM global timer with vexpress, enabled the
  ARM global timer with the A5 and added the definition in the DT. He
  also fixed a invalid check when looking for an usable ARM global
  timer for A9

* Maxime Ripard added the support for AllWinner A31 for sun4i and made
  the timer reset optional through the DT

* Stephen Boyd used the msm timer for the udelay

* Uwe Kleine-König fixed the non-standard 'compatible' binding for efm32

* Xiubo Li clarified the types for the clocksource_mmio_read* and
  added a new Flextimer Module (FTM) with its bindings

* Yang Wei added the 'notrace' attribute to 'read_sched_clock' for the
  dw_apb_timer

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
index deebcd6469fc..02268448dc85 100644
--- a/drivers/clocksource/timer-sun5i.c
+++ b/drivers/clocksource/timer-sun5i.c
@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqreturn.h>
+#include <linux/reset.h>
 #include <linux/sched_clock.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -143,6 +144,7 @@ static u64 sun5i_timer_sched_read(void)
 
 static void __init sun5i_timer_init(struct device_node *node)
 {
+	struct reset_control *rstc;
 	unsigned long rate;
 	struct clk *clk;
 	int ret, irq;
@@ -162,6 +164,10 @@ static void __init sun5i_timer_init(struct device_node *node)
 	clk_prepare_enable(clk);
 	rate = clk_get_rate(clk);
 
+	rstc = of_reset_control_get(node, NULL);
+	if (!IS_ERR(rstc))
+		reset_control_deassert(rstc);
+
 	writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
 	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
 	       timer_base + TIMER_CTL_REG(1));