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| author | Zhen Lei <thunder.leizhen@huawei.com> | 2020-09-18 21:22:36 +0800 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2020-09-24 10:51:04 +0200 |
| commit | 549437a43f45ce70cf5012317633c635c43ba4f4 (patch) | |
| tree | a1d1a8deafd03c00822cd56fbe0d99cf6314f13f /drivers/clocksource/timer-sp.h | |
| parent | bd5a1936ffa2b69032815775fa54fc1c422d49d5 (diff) | |
| download | linux-549437a43f45ce70cf5012317633c635c43ba4f4.tar.bz2 | |
clocksource/drivers/sp804: Enable Hisilicon sp804 timer 64bit mode
A 100MHZ 32-bit timer will be wrapped up less than 43s. Although the
kernel maintains a software high 32-bit count in the tick IRQ. But it's
not applicable to the user mode APPs.
Note: The kernel still uses the lower 32 bits of the timer.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200918132237.3552-9-thunder.leizhen@huawei.com
Diffstat (limited to 'drivers/clocksource/timer-sp.h')
| -rw-r--r-- | drivers/clocksource/timer-sp.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clocksource/timer-sp.h b/drivers/clocksource/timer-sp.h index 1ab75cbed0e0..811f840be0e5 100644 --- a/drivers/clocksource/timer-sp.h +++ b/drivers/clocksource/timer-sp.h @@ -33,12 +33,15 @@ struct sp804_timer { int load; + int load_h; int value; + int value_h; int ctrl; int intclr; int ris; int mis; int bgload; + int bgload_h; int timer_base[NR_TIMERS]; int width; }; @@ -46,12 +49,15 @@ struct sp804_timer { struct sp804_clkevt { void __iomem *base; void __iomem *load; + void __iomem *load_h; void __iomem *value; + void __iomem *value_h; void __iomem *ctrl; void __iomem *intclr; void __iomem *ris; void __iomem *mis; void __iomem *bgload; + void __iomem *bgload_h; unsigned long reload; int width; }; |