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authorDmitry Osipenko <digetx@gmail.com>2019-04-14 22:23:21 +0300
committerStephen Boyd <sboyd@kernel.org>2019-04-25 13:54:23 -0700
commite71f4d385878671991e200083c7d30eb4ca8e99a (patch)
treece71492050855769e843255e002e2360efcd16e7 /drivers/clk
parentf4037654a89906045a1c6a046c35e625524747ce (diff)
downloadlinux-e71f4d385878671991e200083c7d30eb4ca8e99a.tar.bz2
clk: tegra: divider: Mark Memory Controller clock as read-only
The Memory Controller (MC) clock rate can't be simply changed and nothing in kernel need to change the rate, hence let's make the clock read-only. This id also needed for the EMC driver because timing configuration may require the MC clock diver to be disabled, that is handled by the EMC clock / EMC driver integration and CLK framework shall not touch the MC divider configuration on the EMC clock rate change. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-divider.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 205fe8ff63f0..2a1822a22740 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -175,6 +175,7 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
void __iomem *reg, spinlock_t *lock)
{
return clk_register_divider_table(NULL, name, parent_name,
- CLK_IS_CRITICAL, reg, 16, 1, 0,
+ CLK_IS_CRITICAL,
+ reg, 16, 1, CLK_DIVIDER_READ_ONLY,
mc_div_table, lock);
}