diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2018-05-20 16:31:12 +0000 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-06-01 23:21:09 -0700 |
| commit | 7ef3844fc5198065dbe8776798206c10859d209e (patch) | |
| tree | 21599bf7a694a874677ca24f174c4b7ca1f758bc /drivers/clk | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
| download | linux-7ef3844fc5198065dbe8776798206c10859d209e.tar.bz2 | |
clk: ingenic: Add support for clocks whose gate bit is inverted
Support the clocks which are gated when their gate bit is cleared
instead of set.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/ingenic/cgu.c | 5 | ||||
| -rw-r--r-- | drivers/clk/ingenic/cgu.h | 2 |
2 files changed, 5 insertions, 2 deletions
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 56a712c9075f..4b31145eb8aa 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -43,7 +43,8 @@ static inline bool ingenic_cgu_gate_get(struct ingenic_cgu *cgu, const struct ingenic_cgu_gate_info *info) { - return readl(cgu->base + info->reg) & BIT(info->bit); + return !!(readl(cgu->base + info->reg) & BIT(info->bit)) + ^ info->clear_to_gate; } /** @@ -62,7 +63,7 @@ ingenic_cgu_gate_set(struct ingenic_cgu *cgu, { u32 clkgr = readl(cgu->base + info->reg); - if (val) + if (val ^ info->clear_to_gate) clkgr |= BIT(info->bit); else clkgr &= ~BIT(info->bit); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 9da34910bd80..4d2e3fad0e30 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -111,10 +111,12 @@ struct ingenic_cgu_fixdiv_info { * struct ingenic_cgu_gate_info - information about a clock gate * @reg: offset of the gate control register within the CGU * @bit: offset of the bit in the register that controls the gate + * @clear_to_gate: if set, the clock is gated when the bit is cleared */ struct ingenic_cgu_gate_info { unsigned reg; u8 bit; + bool clear_to_gate; }; /** |