diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-06 11:02:35 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-06 11:02:35 -0700 |
| commit | 3cdaeb7d8bd872926cbc0d194a0386e07ce3facb (patch) | |
| tree | 280bf09f69721947fd999f577b49d197bcf2769c /drivers/clk | |
| parent | a444723569b48bc49e3175930eb9777582f48f44 (diff) | |
| parent | 92a847e3609a8d00bcbe8bdfacbcbbca03135410 (diff) | |
| download | linux-3cdaeb7d8bd872926cbc0d194a0386e07ce3facb.tar.bz2 | |
Merge tag 'imx-clk-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull i.MX clk updates from Shawn Guo:
- Update clk-pllv3 driver to get it return correct frequency for
Ethernet PLL on i.MX7D.
- Correct ahb clock mux settings for i.MX7D per latest hardware
document.
* tag 'imx-clk-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx7d: fix ahb clock mux 1
clk: imx: return correct frequency for Ethernet PLL
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-imx7d.c | 2 | ||||
| -rw-r--r-- | drivers/clk/imx/clk-pllv3.c | 9 |
2 files changed, 9 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 7912be83c4af..522996800d5b 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -56,7 +56,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", "pll_audio_main_clk", }; -static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk", +static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk", "pll_video_main_clk", }; diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index c05c43d56a94..4826b3c9e19e 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -44,6 +44,7 @@ struct clk_pllv3 { u32 powerdown; u32 div_mask; u32 div_shift; + unsigned long ref_clock; }; #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) @@ -286,7 +287,9 @@ static const struct clk_ops clk_pllv3_av_ops = { static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - return 500000000; + struct clk_pllv3 *pll = to_clk_pllv3(hw); + + return pll->ref_clock; } static const struct clk_ops clk_pllv3_enet_ops = { @@ -326,7 +329,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, break; case IMX_PLLV3_ENET_IMX7: pll->powerdown = IMX7_ENET_PLL_POWER; + pll->ref_clock = 1000000000; + ops = &clk_pllv3_enet_ops; + break; case IMX_PLLV3_ENET: + pll->ref_clock = 500000000; ops = &clk_pllv3_enet_ops; break; default: |