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authorSean Paul <seanpaul@chromium.org>2014-10-01 12:40:41 -0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2015-02-02 15:46:34 +0200
commitf892f24b37345181b9bc7748ed4a8e927cdb6e06 (patch)
tree75c2f3ba5b9dde77bc4487dad5ad24f8bc2e941b /drivers/clk
parent18abd16376ad88ed3995c63ddae47be78bd56abe (diff)
downloadlinux-f892f24b37345181b9bc7748ed4a8e927cdb6e06.tar.bz2
clk: tegra124: Add init data for dsi lp clocks
Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra124.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index f5f9baca7bb6..5b9bd8a59fe8 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1368,6 +1368,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
{TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
{TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
+ {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
+ {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
{TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
{TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
{TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},