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authorPaul Cercueil <paul@crapouillou.net>2018-05-20 16:31:13 +0000
committerStephen Boyd <sboyd@kernel.org>2018-06-01 23:21:31 -0700
commit261a831f042c906412099e8a4f73d954cb5370b4 (patch)
tree4329e2479b1ce640f04f9d7355a2d84ee5fcbf3a /drivers/clk
parent7ef3844fc5198065dbe8776798206c10859d209e (diff)
downloadlinux-261a831f042c906412099e8a4f73d954cb5370b4.tar.bz2
clk: ingenic: Support specifying "wait for clock stable" delay
Some clocks need a small delay after being ungated to run stable, as using them too soon might result in hardware lockups. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ingenic/cgu.c3
-rw-r--r--drivers/clk/ingenic/cgu.h2
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 4b31145eb8aa..5ef7d9ba2195 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -512,6 +512,9 @@ static int ingenic_clk_enable(struct clk_hw *hw)
spin_lock_irqsave(&cgu->lock, flags);
ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
spin_unlock_irqrestore(&cgu->lock, flags);
+
+ if (clk_info->gate.delay_us)
+ udelay(clk_info->gate.delay_us);
}
return 0;
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 4d2e3fad0e30..542192376ebf 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -112,11 +112,13 @@ struct ingenic_cgu_fixdiv_info {
* @reg: offset of the gate control register within the CGU
* @bit: offset of the bit in the register that controls the gate
* @clear_to_gate: if set, the clock is gated when the bit is cleared
+ * @delay_us: delay in microseconds after which the clock is considered stable
*/
struct ingenic_cgu_gate_info {
unsigned reg;
u8 bit;
bool clear_to_gate;
+ u16 delay_us;
};
/**