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authorPaul Cercueil <paul@crapouillou.net>2020-09-03 03:50:46 +0200
committerStephen Boyd <sboyd@kernel.org>2020-10-13 20:04:50 -0700
commit3860dc599b7d3de869d9d7e2274d2ca8f1e2be86 (patch)
treeedf46c7e0b793b0d54983244794d7f6541c50bdb /drivers/clk
parent21534fe39c494913849f3c46e41282b96bce7df6 (diff)
downloadlinux-3860dc599b7d3de869d9d7e2274d2ca8f1e2be86.tar.bz2
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ingenic/cgu.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 6bb5dedf0252..521a40dfcb72 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -182,6 +182,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
unsigned long rate, flags;
unsigned int m, n, od;
+ int ret = 0;
u32 ctl;
rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,
@@ -203,9 +204,14 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
writel(ctl, cgu->base + pll_info->reg);
+
+ /* If the PLL is enabled, verify that it's stable */
+ if (ctl & BIT(pll_info->enable_bit))
+ ret = ingenic_pll_check_stable(cgu, pll_info);
+
spin_unlock_irqrestore(&cgu->lock, flags);
- return 0;
+ return ret;
}
static int ingenic_pll_enable(struct clk_hw *hw)
@@ -662,7 +668,6 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
}
} else if (caps & CGU_CLK_PLL) {
clk_init.ops = &ingenic_pll_ops;
- clk_init.flags |= CLK_SET_RATE_GATE;
caps &= ~CGU_CLK_PLL;