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| author | Stephen Boyd <sboyd@kernel.org> | 2021-08-24 11:39:04 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-08-24 11:39:04 -0700 |
| commit | 923ba4604a9be794e4ef4911f6c5e15b4bb39b3f (patch) | |
| tree | db2920dc3571964754be9498b8b11d019cfceaf7 /drivers/clk | |
| parent | e73f0f0ee7541171d89f2e2491130c7771ba58d3 (diff) | |
| parent | faa8605f9f92e36c724ecaf03b466cfe31b04b06 (diff) | |
| download | linux-923ba4604a9be794e4ef4911f6c5e15b4bb39b3f.tar.bz2 | |
Merge tag 'for-5.15-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nvidia
Pull a Tegra clk driver cleanup from Thierry Reding:
The FUSE driver has been updated to take manual control of the FUSE
clock over suspend/resume cycles, so the CLK_IS_CRITICAL flag can now be
dropped.
* tag 'for-5.15-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
soc/tegra: fuse: Add runtime PM support
soc/tegra: fuse: Clear fuse->clk on driver probe failure
soc/tegra: pmc: Prevent racing with cpuilde driver
soc/tegra: bpmp: Remove unused including <linux/version.h>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-periph.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 292d6269daf1..4dcf7f7cb8a0 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -777,11 +777,7 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), - /* - * Critical for RAM re-repair operation, which must occur on resume - * from LP1 system suspend and as part of CCPLEX cluster switching. - */ - GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL), + GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), |