diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2021-02-16 14:08:51 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-02-16 14:08:51 -0800 |
| commit | ee6b84a3fc47e01ba5e28a45c78c191da57ff86e (patch) | |
| tree | c058033bf7097b3d7c450a77f6087e6e68589c06 /drivers/clk | |
| parent | 0d7a660bfe79b1bb2cfed710ab159186320de7df (diff) | |
| parent | ee7294ba49bf8559b560b21629ed8153082c25cf (diff) | |
| download | linux-ee6b84a3fc47e01ba5e28a45c78c191da57ff86e.tar.bz2 | |
Merge branch 'clk-unused' into clk-next
- Remove efm32 clk driver
- Remove tango4 clk driver
- Remove zte zx clk driver
- Remove sirf prima2/atlast clk drivers
- Remove u300 clk driver
* clk-unused:
clk: remove u300 driver
clk: remove sirf prima2/atlas drivers
clk: remove zte zx driver
clk: remove tango4 driver
clk: Drop unused efm32gg driver
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/Makefile | 5 | ||||
| -rw-r--r-- | drivers/clk/clk-efm32gg.c | 84 | ||||
| -rw-r--r-- | drivers/clk/clk-tango4.c | 85 | ||||
| -rw-r--r-- | drivers/clk/clk-u300.c | 1199 | ||||
| -rw-r--r-- | drivers/clk/sirf/Makefile | 6 | ||||
| -rw-r--r-- | drivers/clk/sirf/atlas6.h | 32 | ||||
| -rw-r--r-- | drivers/clk/sirf/clk-atlas6.c | 150 | ||||
| -rw-r--r-- | drivers/clk/sirf/clk-atlas7.c | 1682 | ||||
| -rw-r--r-- | drivers/clk/sirf/clk-common.c | 1037 | ||||
| -rw-r--r-- | drivers/clk/sirf/clk-prima2.c | 149 | ||||
| -rw-r--r-- | drivers/clk/sirf/prima2.h | 26 | ||||
| -rw-r--r-- | drivers/clk/zte/Makefile | 4 | ||||
| -rw-r--r-- | drivers/clk/zte/clk-zx296702.c | 741 | ||||
| -rw-r--r-- | drivers/clk/zte/clk-zx296718.c | 1074 | ||||
| -rw-r--r-- | drivers/clk/zte/clk.c | 446 | ||||
| -rw-r--r-- | drivers/clk/zte/clk.h | 174 |
16 files changed, 0 insertions, 6894 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 074e2233f445..5325847469e9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o -obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o @@ -63,9 +62,7 @@ obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o -obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o -obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o @@ -105,7 +102,6 @@ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ -obj-$(CONFIG_ARCH_SIRF) += sirf/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_ARCH_AGILEX) += socfpga/ obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ @@ -123,6 +119,5 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_X86) += x86/ endif obj-y += xilinx/ -obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/ diff --git a/drivers/clk/clk-efm32gg.c b/drivers/clk/clk-efm32gg.c deleted file mode 100644 index 85beaacb4088..000000000000 --- a/drivers/clk/clk-efm32gg.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/io.h> -#include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/slab.h> - -#include <dt-bindings/clock/efm32-cmu.h> - -#define CMU_HFPERCLKEN0 0x44 -#define CMU_MAX_CLKS 37 - -static struct clk_hw_onecell_data *clk_data; - -static void __init efm32gg_cmu_init(struct device_node *np) -{ - int i; - void __iomem *base; - struct clk_hw **hws; - - clk_data = kzalloc(struct_size(clk_data, hws, CMU_MAX_CLKS), - GFP_KERNEL); - - if (!clk_data) - return; - - hws = clk_data->hws; - - for (i = 0; i < CMU_MAX_CLKS; ++i) - hws[i] = ERR_PTR(-ENOENT); - - base = of_iomap(np, 0); - if (!base) { - pr_warn("Failed to map address range for efm32gg,cmu node\n"); - return; - } - - hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0, - 48000000); - - hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0", - "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL); - hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1", - "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL); - hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2", - "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL); - hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0", - "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL); - hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1", - "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL); - hws[clk_HFPERCLKTIMER0] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER0", - "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL); - hws[clk_HFPERCLKTIMER1] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER1", - "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL); - hws[clk_HFPERCLKTIMER2] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER2", - "HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL); - hws[clk_HFPERCLKTIMER3] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER3", - "HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL); - hws[clk_HFPERCLKACMP0] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP0", - "HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL); - hws[clk_HFPERCLKACMP1] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP1", - "HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL); - hws[clk_HFPERCLKI2C0] = clk_hw_register_gate(NULL, "HFPERCLK.I2C0", - "HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL); - hws[clk_HFPERCLKI2C1] = clk_hw_register_gate(NULL, "HFPERCLK.I2C1", - "HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL); - hws[clk_HFPERCLKGPIO] = clk_hw_register_gate(NULL, "HFPERCLK.GPIO", - "HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL); - hws[clk_HFPERCLKVCMP] = clk_hw_register_gate(NULL, "HFPERCLK.VCMP", - "HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL); - hws[clk_HFPERCLKPRS] = clk_hw_register_gate(NULL, "HFPERCLK.PRS", - "HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL); - hws[clk_HFPERCLKADC0] = clk_hw_register_gate(NULL, "HFPERCLK.ADC0", - "HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL); - hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0", - "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL); - - of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); -} -CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init); diff --git a/drivers/clk/clk-tango4.c b/drivers/clk/clk-tango4.c deleted file mode 100644 index fe12a43f7a40..000000000000 --- a/drivers/clk/clk-tango4.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <linux/kernel.h> -#include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <linux/init.h> -#include <linux/io.h> - -#define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */ -static struct clk *clks[CLK_COUNT]; -static struct clk_onecell_data clk_data = { clks, CLK_COUNT }; - -#define SYSCLK_DIV 0x20 -#define CPUCLK_DIV 0x24 -#define DIV_BYPASS BIT(23) - -/*** CLKGEN_PLL ***/ -#define extract_pll_n(val) ((val >> 0) & ((1u << 7) - 1)) -#define extract_pll_k(val) ((val >> 13) & ((1u << 3) - 1)) -#define extract_pll_m(val) ((val >> 16) & ((1u << 3) - 1)) -#define extract_pll_isel(val) ((val >> 24) & ((1u << 3) - 1)) - -static void __init make_pll(int idx, const char *parent, void __iomem *base) -{ - char name[8]; - u32 val, mul, div; - - sprintf(name, "pll%d", idx); - val = readl(base + idx * 8); - mul = extract_pll_n(val) + 1; - div = (extract_pll_m(val) + 1) << extract_pll_k(val); - clk_register_fixed_factor(NULL, name, parent, 0, mul, div); - if (extract_pll_isel(val) != 1) - panic("%s: input not set to XTAL_IN\n", name); -} - -static void __init make_cd(int idx, void __iomem *base) -{ - char name[8]; - u32 val, mul, div; - - sprintf(name, "cd%d", idx); - val = readl(base + idx * 8); - mul = 1 << 27; - div = (2 << 27) + val; - clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div); - if (val > 0xf0000000) - panic("%s: unsupported divider %x\n", name, val); -} - -static void __init tango4_clkgen_setup(struct device_node *np) -{ - struct clk **pp = clk_data.clks; - void __iomem *base = of_iomap(np, 0); - const char *parent = of_clk_get_parent_name(np, 0); - - if (!base) - panic("%pOFn: invalid address\n", np); - - if (readl(base + CPUCLK_DIV) & DIV_BYPASS) - panic("%pOFn: unsupported cpuclk setup\n", np); - - if (readl(base + SYSCLK_DIV) & DIV_BYPASS) - panic("%pOFn: unsupported sysclk setup\n", np); - - writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */ - - make_pll(0, parent, base); - make_pll(1, parent, base); - make_pll(2, parent, base); - make_cd(2, base + 0x80); - make_cd(6, base + 0x80); - - pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0, - base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL); - pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4); - pp[2] = clk_register_fixed_factor(NULL, "usb_clk", "cd2", 0, 1, 2); - pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2); - - if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3])) - panic("%pOFn: clk registration failed\n", np); - - if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) - panic("%pOFn: clk provider registration failed\n", np); -} -CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup); diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c deleted file mode 100644 index e228c07c4c6e..000000000000 --- a/drivers/clk/clk-u300.c +++ /dev/null @@ -1,1199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * U300 clock implementation - * Copyright (C) 2007-2012 ST-Ericsson AB - * Author: Linus Walleij <linus.walleij@stericsson.com> - * Author: Jonas Aaberg <jonas.aberg@stericsson.com> - */ -#include <linux/clkdev.h> -#include <linux/slab.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/clk-provider.h> -#include <linux/spinlock.h> -#include <linux/of.h> -#include <linux/platform_data/clk-u300.h> - -/* APP side SYSCON registers */ -/* CLK Control Register 16bit (R/W) */ -#define U300_SYSCON_CCR (0x0000) -#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) -#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) -#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) -/* CLK Status Register 16bit (R/W) */ -#define U300_SYSCON_CSR (0x0004) -#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) -#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) -/* Reset lines for SLOW devices 16bit (R/W) */ -#define U300_SYSCON_RSR (0x0014) -#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) -#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) -#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) -#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) -#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) -#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) -#define U300_SYSCON_RSR_EH_RESET_EN (0x0008) -#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) -#define U300_SYSCON_RSR_UART_RESET_EN (0x0002) -#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) -/* Reset lines for FAST devices 16bit (R/W) */ -#define U300_SYSCON_RFR (0x0018) -#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) -#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) -#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) -#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) -#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) -#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) -#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) -#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) -/* Reset lines for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_RRR (0x001c) -#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) -#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) -#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) -#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) -#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) -#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) -#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) -#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) -#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) -#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) -#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) -#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) -#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) -/* Clock enable for SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CESR (0x0020) -#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) -#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) -#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) -#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) -#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) -#define U300_SYSCON_CESR_EH_CLK_EN (0x0008) -#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) -#define U300_SYSCON_CESR_UART_CLK_EN (0x0002) -#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) -/* Clock enable for FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CEFR (0x0024) -#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) -#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) -#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) -#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) -#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) -#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) -#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) -#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) -#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) -#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) -/* Clock enable for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CERR (0x0028) -#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) -#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) -#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) -#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) -#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) -#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) -#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) -#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) -#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) -#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) -#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) -#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) -#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) -#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) -/* Single block clock enable 16bit (-/W) */ -#define U300_SYSCON_SBCER (0x002c) -#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) -#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) -#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) -#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) -#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) -#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) -#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) -#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) -#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) -#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) -#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) -#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) -#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) -#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) -#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) -#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) -#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) -#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) -#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) -#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) -#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) -#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) -#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) -#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) -#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) -#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) -#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) -#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) -#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) -#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) -#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) -#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) -#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) -/* Single block clock disable 16bit (-/W) */ -#define U300_SYSCON_SBCDR (0x0030) -/* Same values as above for SBCER */ -/* Clock force SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CFSR (0x003c) -#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) -/* Clock force FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CFFR (0x40) -/* Values not defined. Define if you want to use them. */ -/* Clock force the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CFRR (0x44) -#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) -#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) -#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) -#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) -#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) -#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) -/* PLL208 Frequency Control 16bit (R/W) */ -#define U300_SYSCON_PFCR (0x48) -#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) -/* Power Management Control 16bit (R/W) */ -#define U300_SYSCON_PMCR (0x50) -#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) -#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) -/* Reset Out 16bit (R/W) */ -#define U300_SYSCON_RCR (0x6c) -#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) -/* EMIF Slew Rate Control 16bit (R/W) */ -#define U300_SYSCON_SRCLR (0x70) -#define U300_SYSCON_SRCLR_MASK (0x03FF) -#define U300_SYSCON_SRCLR_VALUE (0x03FF) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) -/* EMIF Clock Control Register 16bit (R/W) */ -#define U300_SYSCON_ECCR (0x0078) -#define U300_SYSCON_ECCR_MASK (0x000F) -#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) -#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) -#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) -#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) -/* MMC/MSPRO frequency divider register 0 16bit (R/W) */ -#define U300_SYSCON_MMF0R (0x90) -#define U300_SYSCON_MMF0R_MASK (0x00FF) -#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) -/* MMC/MSPRO frequency divider register 1 16bit (R/W) */ -#define U300_SYSCON_MMF1R (0x94) -#define U300_SYSCON_MMF1R_MASK (0x00FF) -#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) -/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ -#define U300_SYSCON_MMCR (0x9C) -#define U300_SYSCON_MMCR_MASK (0x0003) -#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) -#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) -/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ -#define U300_SYSCON_S0CCR (0x120) -#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S0CCR_SEL_MCLK (0x8 << 1) -#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA << 1) -#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC << 1) -#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD << 1) -#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE << 1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0 << 1) -#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2 << 1) -#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4 << 1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6 << 1) -/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ -#define U300_SYSCON_S1CCR (0x124) -#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S1CCR_SEL_MCLK (0x8 << 1) -#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA << 1) -#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC << 1) -#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD << 1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE << 1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0 << 1) -#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2 << 1) -#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4 << 1) -#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6 << 1) -/* SYS_2_CLK_CONTROL third clock control 16 bit (R/W) */ -#define U300_SYSCON_S2CCR (0x128) -#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) -#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) -#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S2CCR_SEL_MCLK (0x8 << 1) -#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA << 1) -#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC << 1) -#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD << 1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE << 1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0 << 1) -#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2 << 1) -#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4 << 1) -#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6 << 1) -/* SC_PLL_IRQ_CONTROL 16bit (R/W) */ -#define U300_SYSCON_PICR (0x0130) -#define U300_SYSCON_PICR_MASK (0x00FF) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) -#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) -#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) -#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) -#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) -/* SC_PLL_IRQ_STATUS 16 bit (R/-) */ -#define U300_SYSCON_PISR (0x0134) -#define U300_SYSCON_PISR_MASK (0x000F) -#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) -#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) -#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) -#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) -/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ -#define U300_SYSCON_PICLR (0x0138) -#define U300_SYSCON_PICLR_MASK (0x000F) -#define U300_SYSCON_PICLR_RWMASK (0x0000) -#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) -#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) -#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) -#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) -/* Clock activity observability register 0 */ -#define U300_SYSCON_C0OAR (0x140) -#define U300_SYSCON_C0OAR_MASK (0xFFFF) -#define U300_SYSCON_C0OAR_VALUE (0xFFFF) -#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) -#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) -#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) -#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) -#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) -#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) -#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) -#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) -#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) -#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) -#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) -#define U300_SYSCON_C0OAR_APEX_CLK (0x0010) -#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) -#define U300_SYSCON_C0OAR_AHB_CLK (0x0004) -#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) -#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) -/* Clock activity observability register 1 */ -#define U300_SYSCON_C1OAR (0x144) -#define U300_SYSCON_C1OAR_MASK (0x3FFE) -#define U300_SYSCON_C1OAR_VALUE (0x3FFE) -#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) -#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) -#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) -#define U300_SYSCON_C1OAR_MMC_CLK (0x0400) -#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) -#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) -#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) -#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) -#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) -#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) -#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) -#define U300_SYSCON_C1OAR_PPM_CLK (0x0004) -#define U300_SYSCON_C1OAR_DMA_CLK (0x0002) -/* Clock activity observability register 2 */ -#define U300_SYSCON_C2OAR (0x148) -#define U300_SYSCON_C2OAR_MASK (0x0FFF) -#define U300_SYSCON_C2OAR_VALUE (0x0FFF) -#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) -#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) -#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) -#define U300_SYSCON_C2OAR_VC_CLK (0x0100) -#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) -#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) -#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) -#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) -#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) -#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) -#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) -#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) - - -/* - * The clocking hierarchy currently looks like this. - * NOTE: the idea is NOT to show how the clocks are routed on the chip! - * The ideas is to show dependencies, so a clock higher up in the - * hierarchy has to be on in order for another clock to be on. Now, - * both CPU and DMA can actually be on top of the hierarchy, and that - * is not modeled currently. Instead we have the backbone AMBA bus on - * top. This bus cannot be programmed in any way but conceptually it - * needs to be active for the bridges and devices to transport data. - * - * Please be aware that a few clocks are hw controlled, which mean that - * the hw itself can turn on/off or change the rate of the clock when - * needed! - * - * AMBA bus - * | - * +- CPU - * +- FSMC NANDIF NAND Flash interface - * +- SEMI Shared Memory interface - * +- ISP Image Signal Processor (U335 only) - * +- CDS (U335 only) - * +- DMA Direct Memory Access Controller - * +- AAIF APP/ACC Interface (Mobile Scalable Link, MSL) - * +- APEX - * +- VIDEO_ENC AVE2/3 Video Encoder - * +- XGAM Graphics Accelerator Controller - * +- AHB - * | - * +- ahb:0 AHB Bridge - * | | - * | +- ahb:1 INTCON Interrupt controller - * | +- ahb:3 MSPRO Memory Stick Pro controller - * | +- ahb:4 EMIF External Memory interface - * | - * +- fast:0 FAST bridge - * | | - * | +- fast:1 MMCSD MMC/SD card reader controller - * | +- fast:2 I2S0 PCM I2S channel 0 controller - * | +- fast:3 I2S1 PCM I2S channel 1 controller - * | +- fast:4 I2C0 I2C channel 0 controller - * | +- fast:5 I2C1 I2C channel 1 controller - * | +- fast:6 SPI SPI controller - * | +- fast:7 UART1 Secondary UART (U335 only) - * | - * +- slow:0 SLOW bridge - * | - * +- slow:1 SYSCON (not possible to control) - * +- slow:2 WDOG Watchdog - * +- slow:3 UART0 primary UART - * +- slow:4 TIMER_APP Application timer - used in Linux - * +- slow:5 KEYPAD controller - * +- slow:6 GPIO controller - * +- slow:7 RTC controller - * +- slow:8 BT Bus Tracer (not used currently) - * +- slow:9 EH Event Handler (not used currently) - * +- slow:a TIMER_ACC Access style timer (not used currently) - * +- slow:b PPM (U335 only, what is that?) - */ - -/* Global syscon virtual base */ -static void __iomem *syscon_vbase; - -/** - * struct clk_syscon - U300 syscon clock - * @hw: corresponding clock hardware entry - * @hw_ctrld: whether this clock is hardware controlled (for refcount etc) - * and does not need any magic pokes to be enabled/disabled - * @reset: state holder, whether this block's reset line is asserted or not - * @res_reg: reset line enable/disable flag register - * @res_bit: bit for resetting or taking this consumer out of reset - * @en_reg: clock line enable/disable flag register - * @en_bit: bit for enabling/disabling this consumer clock line - * @clk_val: magic value to poke in the register to enable/disable - * this one clock - */ -struct clk_syscon { - struct clk_hw hw; - bool hw_ctrld; - bool reset; - void __iomem *res_reg; - u8 res_bit; - void __iomem *en_reg; - u8 en_bit; - u16 clk_val; -}; - -#define to_syscon(_hw) container_of(_hw, struct clk_syscon, hw) - -static DEFINE_SPINLOCK(syscon_resetreg_lock); - -/* - * Reset control functions. We remember if a block has been - * taken out of reset and don't remove the reset assertion again - * and vice versa. Currently we only remove resets so the - * enablement function is defined out. - */ -static void syscon_block_reset_enable(struct clk_syscon *sclk) -{ - unsigned long iflags; - u16 val; - - /* Not all blocks support resetting */ - if (!sclk->res_reg) - return; - spin_lock_irqsave(&syscon_resetreg_lock, iflags); - val = readw(sclk->res_reg); - val |= BIT(sclk->res_bit); - writew(val, sclk->res_reg); - spin_unlock_irqrestore(&syscon_resetreg_lock, iflags); - sclk->reset = true; -} - -static void syscon_block_reset_disable(struct clk_syscon *sclk) -{ - unsigned long iflags; - u16 val; - - /* Not all blocks support resetting */ - if (!sclk->res_reg) - return; - spin_lock_irqsave(&syscon_resetreg_lock, iflags); - val = readw(sclk->res_reg); - val &= ~BIT(sclk->res_bit); - writew(val, sclk->res_reg); - spin_unlock_irqrestore(&syscon_resetreg_lock, iflags); - sclk->reset = false; -} - -static int syscon_clk_prepare(struct clk_hw *hw) -{ - struct clk_syscon *sclk = to_syscon(hw); - - /* If the block is in reset, bring it out */ - if (sclk->reset) - syscon_block_reset_disable(sclk); - return 0; -} - -static void syscon_clk_unprepare(struct clk_hw *hw) -{ - struct clk_syscon *sclk = to_syscon(hw); - - /* Please don't force the console into reset */ - if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN) - return; - /* When unpreparing, force block into reset */ - if (!sclk->reset) - syscon_block_reset_enable(sclk); -} - -static int syscon_clk_enable(struct clk_hw *hw) -{ - struct clk_syscon *sclk = to_syscon(hw); - - /* Don't touch the hardware controlled clocks */ - if (sclk->hw_ctrld) - return 0; - /* These cannot be controlled */ - if (sclk->clk_val == 0xFFFFU) - return 0; - - writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER); - return 0; -} - -static void syscon_clk_disable(struct clk_hw *hw) -{ - struct clk_syscon *sclk = to_syscon(hw); - - /* Don't touch the hardware controlled clocks */ - if (sclk->hw_ctrld) - return; - if (sclk->clk_val == 0xFFFFU) - return; - /* Please don't disable the console port */ - if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN) - return; - - writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR); -} - -static int syscon_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_syscon *sclk = to_syscon(hw); - u16 val; - - /* If no enable register defined, it's always-on */ - if (!sclk->en_reg) - return 1; - - val = readw(sclk->en_reg); - val &= BIT(sclk->en_bit); - - return val ? 1 : 0; -} - -static u16 syscon_get_perf(void) -{ - u16 val; - - val = readw(syscon_vbase + U300_SYSCON_CCR); - val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; - return val; -} - -static unsigned long -syscon_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_syscon *sclk = to_syscon(hw); - u16 perf = syscon_get_perf(); - - switch (sclk->clk_val) { - case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN: - case U300_SYSCON_SBCER_I2C0_CLK_EN: - case U300_SYSCON_SBCER_I2C1_CLK_EN: - case U300_SYSCON_SBCER_MMC_CLK_EN: - case U300_SYSCON_SBCER_SPI_CLK_EN: - /* The FAST clocks have one progression */ - switch (perf) { - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: - return 13000000; - default: - return parent_rate; /* 26 MHz */ - } - case U300_SYSCON_SBCER_DMAC_CLK_EN: - case U300_SYSCON_SBCER_NANDIF_CLK_EN: - case U300_SYSCON_SBCER_XGAM_CLK_EN: - /* AMBA interconnect peripherals */ - switch (perf) { - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: - return 6500000; - case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: - return 26000000; - default: - return parent_rate; /* 52 MHz */ - } - case U300_SYSCON_SBCER_SEMI_CLK_EN: - case U300_SYSCON_SBCER_EMIF_CLK_EN: - /* EMIF speeds */ - switch (perf) { - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: - return 13000000; - case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: - return 52000000; - default: - return 104000000; - } - case U300_SYSCON_SBCER_CPU_CLK_EN: - /* And the fast CPU clock */ - switch (perf) { - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: - return 13000000; - case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: - return 52000000; - case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: - return 104000000; - default: - return parent_rate; /* 208 MHz */ - } - default: - /* - * The SLOW clocks and default just inherit the rate of - * their parent (typically PLL13 13 MHz). - */ - return parent_rate; - } -} - -static long -syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_syscon *sclk = to_syscon(hw); - - if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN) - return *prate; - /* We really only support setting the rate of the CPU clock */ - if (rate <= 13000000) - return 13000000; - if (rate <= 52000000) - return 52000000; - if (rate <= 104000000) - return 104000000; - return 208000000; -} - -static int syscon_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_syscon *sclk = to_syscon(hw); - u16 val; - - /* We only support setting the rate of the CPU clock */ - if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN) - return -EINVAL; - switch (rate) { - case 13000000: - val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER; - break; - case 52000000: - val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE; - break; - case 104000000: - val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH; - break; - case 208000000: - val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST; - break; - default: - return -EINVAL; - } - val |= readw(syscon_vbase + U300_SYSCON_CCR) & - ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ; - writew(val, syscon_vbase + U300_SYSCON_CCR); - return 0; -} - -static const struct clk_ops syscon_clk_ops = { - .prepare = syscon_clk_prepare, - .unprepare = syscon_clk_unprepare, - .enable = syscon_clk_enable, - .disable = syscon_clk_disable, - .is_enabled = syscon_clk_is_enabled, - .recalc_rate = syscon_clk_recalc_rate, - .round_rate = syscon_clk_round_rate, - .set_rate = syscon_clk_set_rate, -}; - -static struct clk_hw * __init -syscon_clk_register(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, - bool hw_ctrld, - void __iomem *res_reg, u8 res_bit, - void __iomem *en_reg, u8 en_bit, - u16 clk_val) -{ - struct clk_hw *hw; - struct clk_syscon *sclk; - struct clk_init_data init; - int ret; - - sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); - if (!sclk) - return ERR_PTR(-ENOMEM); - - init.name = name; - init.ops = &syscon_clk_ops; - init.flags = flags; - init.parent_names = (parent_name ? &parent_name : NULL); - init.num_parents = (parent_name ? 1 : 0); - sclk->hw.init = &init; - sclk->hw_ctrld = hw_ctrld; - /* Assume the block is in reset at registration */ - sclk->reset = true; - sclk->res_reg = res_reg; - sclk->res_bit = res_bit; - sclk->en_reg = en_reg; - sclk->en_bit = en_bit; - sclk->clk_val = clk_val; - - hw = &sclk->hw; - ret = clk_hw_register(dev, hw); - if (ret) { - kfree(sclk); - hw = ERR_PTR(ret); - } - - return hw; -} - -#define U300_CLK_TYPE_SLOW 0 -#define U300_CLK_TYPE_FAST 1 -#define U300_CLK_TYPE_REST 2 - -/** - * struct u300_clock - defines the bits and pieces for a certain clock - * @type: the clock type, slow fast or rest - * @id: the bit in the slow/fast/rest register for this clock - * @hw_ctrld: whether the clock is hardware controlled - * @clk_val: a value to poke in the one-write enable/disable registers - */ -struct u300_clock { - u8 type; - u8 id; - bool hw_ctrld; - u16 clk_val; -}; - -static struct u300_clock const u300_clk_lookup[] __initconst = { - { - .type = U300_CLK_TYPE_REST, - .id = 3, - .hw_ctrld = true, - .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN, - }, - { - .type = U300_CLK_TYPE_REST, - .id = 4, - .hw_ctrld = true, - .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN, - }, - { - .type = U300_CLK_TYPE_REST, - .id = 5, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN, - }, - { - .type = U300_CLK_TYPE_REST, - .id = 6, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN, - }, - { - .type = U300_CLK_TYPE_REST, - .id = 8, - .hw_ctrld = true, - .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN, - }, - { - .type = U300_CLK_TYPE_REST, - .id = 9, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN, - }, - { - .type = U300_CLK_TYPE_REST, - .id = 10, - .hw_ctrld = true, - .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN, - }, - { - .type = U300_CLK_TYPE_REST, - .id = 12, - .hw_ctrld = false, - /* INTCON: cannot be enabled, just taken out of reset */ - .clk_val = 0xFFFFU, - }, - { - .type = U300_CLK_TYPE_FAST, - .id = 0, - .hw_ctrld = true, - .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN, - }, - { - .type = U300_CLK_TYPE_FAST, - .id = 1, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN, - }, - { - .type = U300_CLK_TYPE_FAST, - .id = 2, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN, - }, - { - .type = U300_CLK_TYPE_FAST, - .id = 5, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN, - }, - { - .type = U300_CLK_TYPE_FAST, - .id = 6, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN, - }, - { - .type = U300_CLK_TYPE_SLOW, - .id = 0, - .hw_ctrld = true, - .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN, - }, - { - .type = U300_CLK_TYPE_SLOW, - .id = 1, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, - }, - { - .type = U300_CLK_TYPE_SLOW, - .id = 4, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN, - }, - { - .type = U300_CLK_TYPE_SLOW, - .id = 6, - .hw_ctrld = true, - /* No clock enable register bit */ - .clk_val = 0xFFFFU, - }, - { - .type = U300_CLK_TYPE_SLOW, - .id = 7, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN, - }, - { - .type = U300_CLK_TYPE_SLOW, - .id = 8, - .hw_ctrld = false, - .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN, - }, -}; - -static void __init of_u300_syscon_clk_init(struct device_node *np) -{ - struct clk_hw *hw = ERR_PTR(-EINVAL); - const char *clk_name = np->name; - const char *parent_name; - void __iomem *res_reg; - void __iomem *en_reg; - u32 clk_type; - u32 clk_id; - int i; - - if (of_property_read_u32(np, "clock-type", &clk_type)) { - pr_err("%s: syscon clock \"%s\" missing clock-type property\n", - __func__, clk_name); - return; - } - if (of_property_read_u32(np, "clock-id", &clk_id)) { - pr_err("%s: syscon clock \"%s\" missing clock-id property\n", - __func__, clk_name); - return; - } - parent_name = of_clk_get_parent_name(np, 0); - - switch (clk_type) { - case U300_CLK_TYPE_SLOW: - res_reg = syscon_vbase + U300_SYSCON_RSR; - en_reg = syscon_vbase + U300_SYSCON_CESR; - break; - case U300_CLK_TYPE_FAST: - res_reg = syscon_vbase + U300_SYSCON_RFR; - en_reg = syscon_vbase + U300_SYSCON_CEFR; - break; - case U300_CLK_TYPE_REST: - res_reg = syscon_vbase + U300_SYSCON_RRR; - en_reg = syscon_vbase + U300_SYSCON_CERR; - break; - default: - pr_err("unknown clock type %x specified\n", clk_type); - return; - } - - for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) { - const struct u300_clock *u3clk = &u300_clk_lookup[i]; - - if (u3clk->type == clk_type && u3clk->id == clk_id) - hw = syscon_clk_register(NULL, clk_name, parent_name, - 0, u3clk->hw_ctrld, - res_reg, u3clk->id, - en_reg, u3clk->id, - u3clk->clk_val); - } - - if (!IS_ERR(hw)) { - of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); - - /* - * Some few system clocks - device tree does not - * represent clocks without a corresponding device node. - * for now we add these three clocks here. - */ - if (clk_type == U300_CLK_TYPE_REST && clk_id == 5) - clk_hw_register_clkdev(hw, NULL, "pl172"); - if (clk_type == U300_CLK_TYPE_REST && clk_id == 9) - clk_hw_register_clkdev(hw, NULL, "semi"); - if (clk_type == U300_CLK_TYPE_REST && clk_id == 12) - clk_hw_register_clkdev(hw, NULL, "intcon"); - } -} - -/** - * struct clk_mclk - U300 MCLK clock (MMC/SD clock) - * @hw: corresponding clock hardware entry - * @is_mspro: if this is the memory stick clock rather than MMC/SD - */ -struct clk_mclk { - struct clk_hw hw; - bool is_mspro; -}; - -#define to_mclk(_hw) container_of(_hw, struct clk_mclk, hw) - -static int mclk_clk_prepare(struct clk_hw *hw) -{ - struct clk_mclk *mclk = to_mclk(hw); - u16 val; - - /* The MMC and MSPRO clocks need some special set-up */ - if (!mclk->is_mspro) { - /* Set default MMC clock divisor to 18.9 MHz */ - writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R); - val = readw(syscon_vbase + U300_SYSCON_MMCR); - /* Disable the MMC feedback clock */ - val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; - /* Disable MSPRO frequency */ - val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; - writew(val, syscon_vbase + U300_SYSCON_MMCR); - } else { - val = readw(syscon_vbase + U300_SYSCON_MMCR); - /* Disable the MMC feedback clock */ - val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE; - /* Enable MSPRO frequency */ - val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE; - writew(val, syscon_vbase + U300_SYSCON_MMCR); - } - - return 0; -} - -static unsigned long -mclk_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - u16 perf = syscon_get_perf(); - - switch (perf) { - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: - /* - * Here, the 208 MHz PLL gets shut down and the always - * on 13 MHz PLL used for RTC etc kicks into use - * instead. - */ - return 13000000; - case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: - case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE: - case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH: - case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST: - { - /* - * This clock is under program control. The register is - * divided in two nybbles, bit 7-4 gives cycles-1 to count - * high, bit 3-0 gives cycles-1 to count low. Distribute - * these with no more than 1 cycle difference between - * low and high and add low and high to get the actual - * divisor. The base PLL is 208 MHz. Writing 0x00 will - * divide by 1 and 1 so the highest frequency possible - * is 104 MHz. - * - * e.g. 0x54 => - * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz - */ - u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) & - U300_SYSCON_MMF0R_MASK; - switch (val) { - case 0x0054: - return 18900000; - case 0x0044: - return 20800000; - case 0x0043: - return 23100000; - case 0x0033: - return 26000000; - case 0x0032: - return 29700000; - case 0x0022: - return 34700000; - case 0x0021: - return 41600000; - case 0x0011: - return 52000000; - case 0x0000: - return 104000000; - default: - break; - } - } - default: - break; - } - return parent_rate; -} - -static long -mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - if (rate <= 18900000) - return 18900000; - if (rate <= 20800000) - return 20800000; - if (rate <= 23100000) - return 23100000; - if (rate <= 26000000) - return 26000000; - if (rate <= 29700000) - return 29700000; - if (rate <= 34700000) - return 34700000; - if (rate <= 41600000) - return 41600000; - /* Highest rate */ - return 52000000; -} - -static int mclk_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - u16 val; - u16 reg; - - switch (rate) { - case 18900000: - val = 0x0054; - break; - case 20800000: - val = 0x0044; - break; - case 23100000: - val = 0x0043; - break; - case 26000000: - val = 0x0033; - break; - case 29700000: - val = 0x0032; - break; - case 34700000: - val = 0x0022; - break; - case 41600000: - val = 0x0021; - break; - case 52000000: - val = 0x0011; - break; - case 104000000: - val = 0x0000; - break; - default: - return -EINVAL; - } - - reg = readw(syscon_vbase + U300_SYSCON_MMF0R) & - ~U300_SYSCON_MMF0R_MASK; - writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R); - return 0; -} - -static const struct clk_ops mclk_ops = { - .prepare = mclk_clk_prepare, - .recalc_rate = mclk_clk_recalc_rate, - .round_rate = mclk_clk_round_rate, - .set_rate = mclk_clk_set_rate, -}; - -static struct clk_hw * __init -mclk_clk_register(struct device *dev, const char *name, - const char *parent_name, bool is_mspro) -{ - struct clk_hw *hw; - struct clk_mclk *mclk; - struct clk_init_data init; - int ret; - - mclk = kzalloc(sizeof(*mclk), GFP_KERNEL); - if (!mclk) - return ERR_PTR(-ENOMEM); - - init.name = "mclk"; - init.ops = &mclk_ops; - init.flags = 0; - init.parent_names = (parent_name ? &parent_name : NULL); - init.num_parents = (parent_name ? 1 : 0); - mclk->hw.init = &init; - mclk->is_mspro = is_mspro; - - hw = &mclk->hw; - ret = clk_hw_register(dev, hw); - if (ret) { - kfree(mclk); - hw = ERR_PTR(ret); - } - - return hw; -} - -static void __init of_u300_syscon_mclk_init(struct device_node *np) -{ - struct clk_hw *hw; - const char *clk_name = np->name; - const char *parent_name; - - parent_name = of_clk_get_parent_name(np, 0); - hw = mclk_clk_register(NULL, clk_name, parent_name, false); - if (!IS_ERR(hw)) - of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); -} - -static const struct of_device_id u300_clk_match[] __initconst = { - { - .compatible = "fixed-clock", - .data = of_fixed_clk_setup, - }, - { - .compatible = "fixed-factor-clock", - .data = of_fixed_factor_clk_setup, - }, - { - .compatible = "stericsson,u300-syscon-clk", - .data = of_u300_syscon_clk_init, - }, - { - .compatible = "stericsson,u300-syscon-mclk", - .data = of_u300_syscon_mclk_init, - }, - {} -}; - - -void __init u300_clk_init(void __iomem *base) -{ - u16 val; - - syscon_vbase = base; - - /* Set system to run at PLL208, max performance, a known state. */ - val = readw(syscon_vbase + U300_SYSCON_CCR); - val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK; - writew(val, syscon_vbase + U300_SYSCON_CCR); - /* Wait for the PLL208 to lock if not locked in yet */ - while (!(readw(syscon_vbase + U300_SYSCON_CSR) & - U300_SYSCON_CSR_PLL208_LOCK_IND)); - - /* Power management enable */ - val = readw(syscon_vbase + U300_SYSCON_PMCR); - val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; - writew(val, syscon_vbase + U300_SYSCON_PMCR); - - of_clk_init(u300_clk_match); -} diff --git a/drivers/clk/sirf/Makefile b/drivers/clk/sirf/Makefile deleted file mode 100644 index 0ff61f87cddb..000000000000 --- a/drivers/clk/sirf/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for sirf specific clk -# - -obj-$(CONFIG_ARCH_SIRF) += clk-prima2.o clk-atlas6.o clk-atlas7.o diff --git a/drivers/clk/sirf/atlas6.h b/drivers/clk/sirf/atlas6.h deleted file mode 100644 index cb871e30a175..000000000000 --- a/drivers/clk/sirf/atlas6.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define SIRFSOC_CLKC_CLK_EN0 0x0000 -#define SIRFSOC_CLKC_CLK_EN1 0x0004 -#define SIRFSOC_CLKC_REF_CFG 0x0020 -#define SIRFSOC_CLKC_CPU_CFG 0x0024 -#define SIRFSOC_CLKC_MEM_CFG 0x0028 -#define SIRFSOC_CLKC_MEMDIV_CFG 0x002C -#define SIRFSOC_CLKC_SYS_CFG 0x0030 -#define SIRFSOC_CLKC_IO_CFG 0x0034 -#define SIRFSOC_CLKC_DSP_CFG 0x0038 -#define SIRFSOC_CLKC_GFX_CFG 0x003c -#define SIRFSOC_CLKC_MM_CFG 0x0040 -#define SIRFSOC_CLKC_GFX2D_CFG 0x0040 -#define SIRFSOC_CLKC_LCD_CFG 0x0044 -#define SIRFSOC_CLKC_MMC01_CFG 0x0048 -#define SIRFSOC_CLKC_MMC23_CFG 0x004C -#define SIRFSOC_CLKC_MMC45_CFG 0x0050 -#define SIRFSOC_CLKC_NAND_CFG 0x0054 -#define SIRFSOC_CLKC_NANDDIV_CFG 0x0058 -#define SIRFSOC_CLKC_PLL1_CFG0 0x0080 -#define SIRFSOC_CLKC_PLL2_CFG0 0x0084 -#define SIRFSOC_CLKC_PLL3_CFG0 0x0088 -#define SIRFSOC_CLKC_PLL1_CFG1 0x008c -#define SIRFSOC_CLKC_PLL2_CFG1 0x0090 -#define SIRFSOC_CLKC_PLL3_CFG1 0x0094 -#define SIRFSOC_CLKC_PLL1_CFG2 0x0098 -#define SIRFSOC_CLKC_PLL2_CFG2 0x009c -#define SIRFSOC_CLKC_PLL3_CFG2 0x00A0 -#define SIRFSOC_USBPHY_PLL_CTRL 0x0008 -#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) -#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) -#define SIRFSOC_USBPHY_PLL_LOCK BIT(3) diff --git a/drivers/clk/sirf/clk-atlas6.c b/drivers/clk/sirf/clk-atlas6.c deleted file mode 100644 index b95483bb6a5e..000000000000 --- a/drivers/clk/sirf/clk-atlas6.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Clock tree for CSR SiRFatlasVI - * - * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group - * company. - */ - -#include <linux/module.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <linux/syscore_ops.h> - -#include "atlas6.h" -#include "clk-common.c" - -static struct clk_dmn clk_mmc01 = { - .regofs = SIRFSOC_CLKC_MMC01_CFG, - .enable_bit = 59, - .hw = { - .init = &clk_mmc01_init, - }, -}; - -static struct clk_dmn clk_mmc23 = { - .regofs = SIRFSOC_CLKC_MMC23_CFG, - .enable_bit = 60, - .hw = { - .init = &clk_mmc23_init, - }, -}; - -static struct clk_dmn clk_mmc45 = { - .regofs = SIRFSOC_CLKC_MMC45_CFG, - .enable_bit = 61, - .hw = { - .init = &clk_mmc45_init, - }, -}; - -static const struct clk_init_data clk_nand_init = { - .name = "nand", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_nand = { - .regofs = SIRFSOC_CLKC_NAND_CFG, - .enable_bit = 34, - .hw = { - .init = &clk_nand_init, - }, -}; - -enum atlas6_clk_index { - /* 0 1 2 3 4 5 6 7 8 9 */ - rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, - mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0, - spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1, - usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll, - usb0, usb1, cphif, maxclk, -}; - -static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = { - NULL, /* dummy */ - NULL, - &clk_pll1.hw, - &clk_pll2.hw, - &clk_pll3.hw, - &clk_mem.hw, - &clk_sys.hw, - &clk_security.hw, - &clk_dsp.hw, - &clk_gps.hw, - &clk_mf.hw, - &clk_io.hw, - &clk_cpu.hw, - &clk_uart0.hw, - &clk_uart1.hw, - &clk_uart2.hw, - &clk_tsc.hw, - &clk_i2c0.hw, - &clk_i2c1.hw, - &clk_spi0.hw, - &clk_spi1.hw, - &clk_pwmc.hw, - &clk_efuse.hw, - &clk_pulse.hw, - &clk_dmac0.hw, - &clk_dmac1.hw, - &clk_nand.hw, - &clk_audio.hw, - &clk_usp0.hw, - &clk_usp1.hw, - &clk_usp2.hw, - &clk_vip.hw, - &clk_gfx.hw, - &clk_gfx2d.hw, - &clk_lcd.hw, - &clk_vpp.hw, - &clk_mmc01.hw, - &clk_mmc23.hw, - &clk_mmc45.hw, - &usb_pll_clk_hw, - &clk_usb0.hw, - &clk_usb1.hw, - &clk_cphif.hw, -}; - -static struct clk *atlas6_clks[maxclk]; - -static void __init atlas6_clk_init(struct device_node *np) -{ - struct device_node *rscnp; - int i; - - rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); - sirfsoc_rsc_vbase = of_iomap(rscnp, 0); - if (!sirfsoc_rsc_vbase) - panic("unable to map rsc registers\n"); - of_node_put(rscnp); - - sirfsoc_clk_vbase = of_iomap(np, 0); - if (!sirfsoc_clk_vbase) - panic("unable to map clkc registers\n"); - - /* These are always available (RTC and 26MHz OSC)*/ - atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768); - atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0, - 26000000); - - for (i = pll1; i < maxclk; i++) { - atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]); - BUG_ON(IS_ERR(atlas6_clks[i])); - } - clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu"); - clk_register_clkdev(atlas6_clks[io], NULL, "io"); - clk_register_clkdev(atlas6_clks[mem], NULL, "mem"); - clk_register_clkdev(atlas6_clks[mem], NULL, "osc"); - - clk_data.clks = atlas6_clks; - clk_data.clk_num = maxclk; - - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -} -CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init); diff --git a/drivers/clk/sirf/clk-atlas7.c b/drivers/clk/sirf/clk-atlas7.c deleted file mode 100644 index 3f57fefd13bb..000000000000 --- a/drivers/clk/sirf/clk-atlas7.c +++ /dev/null @@ -1,1682 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Clock tree for CSR SiRFAtlas7 - * - * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. - */ - -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/clk-provider.h> -#include <linux/delay.h> -#include <linux/of_address.h> -#include <linux/reset-controller.h> -#include <linux/slab.h> - -#define SIRFSOC_CLKC_MEMPLL_AB_FREQ 0x0000 -#define SIRFSOC_CLKC_MEMPLL_AB_SSC 0x0004 -#define SIRFSOC_CLKC_MEMPLL_AB_CTRL0 0x0008 -#define SIRFSOC_CLKC_MEMPLL_AB_CTRL1 0x000c -#define SIRFSOC_CLKC_MEMPLL_AB_STATUS 0x0010 -#define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_ADDR 0x0014 -#define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_DATA 0x0018 - -#define SIRFSOC_CLKC_CPUPLL_AB_FREQ 0x001c -#define SIRFSOC_CLKC_CPUPLL_AB_SSC 0x0020 -#define SIRFSOC_CLKC_CPUPLL_AB_CTRL0 0x0024 -#define SIRFSOC_CLKC_CPUPLL_AB_CTRL1 0x0028 -#define SIRFSOC_CLKC_CPUPLL_AB_STATUS 0x002c - -#define SIRFSOC_CLKC_SYS0PLL_AB_FREQ 0x0030 -#define SIRFSOC_CLKC_SYS0PLL_AB_SSC 0x0034 -#define SIRFSOC_CLKC_SYS0PLL_AB_CTRL0 0x0038 -#define SIRFSOC_CLKC_SYS0PLL_AB_CTRL1 0x003c -#define SIRFSOC_CLKC_SYS0PLL_AB_STATUS 0x0040 - -#define SIRFSOC_CLKC_SYS1PLL_AB_FREQ 0x0044 -#define SIRFSOC_CLKC_SYS1PLL_AB_SSC 0x0048 -#define SIRFSOC_CLKC_SYS1PLL_AB_CTRL0 0x004c -#define SIRFSOC_CLKC_SYS1PLL_AB_CTRL1 0x0050 -#define SIRFSOC_CLKC_SYS1PLL_AB_STATUS 0x0054 - -#define SIRFSOC_CLKC_SYS2PLL_AB_FREQ 0x0058 -#define SIRFSOC_CLKC_SYS2PLL_AB_SSC 0x005c -#define SIRFSOC_CLKC_SYS2PLL_AB_CTRL0 0x0060 -#define SIRFSOC_CLKC_SYS2PLL_AB_CTRL1 0x0064 -#define SIRFSOC_CLKC_SYS2PLL_AB_STATUS 0x0068 - -#define SIRFSOC_CLKC_SYS3PLL_AB_FREQ 0x006c -#define SIRFSOC_CLKC_SYS3PLL_AB_SSC 0x0070 -#define SIRFSOC_CLKC_SYS3PLL_AB_CTRL0 0x0074 -#define SIRFSOC_CLKC_SYS3PLL_AB_CTRL1 0x0078 -#define SIRFSOC_CLKC_SYS3PLL_AB_STATUS 0x007c - -#define SIRFSOC_ABPLL_CTRL0_SSEN 0x00001000 -#define SIRFSOC_ABPLL_CTRL0_BYPASS 0x00000010 -#define SIRFSOC_ABPLL_CTRL0_RESET 0x00000001 - -#define SIRFSOC_CLKC_AUDIO_DTO_INC 0x0088 -#define SIRFSOC_CLKC_DISP0_DTO_INC 0x008c -#define SIRFSOC_CLKC_DISP1_DTO_INC 0x0090 - -#define SIRFSOC_CLKC_AUDIO_DTO_SRC 0x0094 -#define SIRFSOC_CLKC_AUDIO_DTO_ENA 0x0098 -#define SIRFSOC_CLKC_AUDIO_DTO_DROFF 0x009c - -#define SIRFSOC_CLKC_DISP0_DTO_SRC 0x00a0 -#define SIRFSOC_CLKC_DISP0_DTO_ENA 0x00a4 -#define SIRFSOC_CLKC_DISP0_DTO_DROFF 0x00a8 - -#define SIRFSOC_CLKC_DISP1_DTO_SRC 0x00ac -#define SIRFSOC_CLKC_DISP1_DTO_ENA 0x00b0 -#define SIRFSOC_CLKC_DISP1_DTO_DROFF 0x00b4 - -#define SIRFSOC_CLKC_I2S_CLK_SEL 0x00b8 -#define SIRFSOC_CLKC_I2S_SEL_STAT 0x00bc - -#define SIRFSOC_CLKC_USBPHY_CLKDIV_CFG 0x00c0 -#define SIRFSOC_CLKC_USBPHY_CLKDIV_ENA 0x00c4 -#define SIRFSOC_CLKC_USBPHY_CLK_SEL 0x00c8 -#define SIRFSOC_CLKC_USBPHY_CLK_SEL_STAT 0x00cc - -#define SIRFSOC_CLKC_BTSS_CLKDIV_CFG 0x00d0 -#define SIRFSOC_CLKC_BTSS_CLKDIV_ENA 0x00d4 -#define SIRFSOC_CLKC_BTSS_CLK_SEL 0x00d8 -#define SIRFSOC_CLKC_BTSS_CLK_SEL_STAT 0x00dc - -#define SIRFSOC_CLKC_RGMII_CLKDIV_CFG 0x00e0 -#define SIRFSOC_CLKC_RGMII_CLKDIV_ENA 0x00e4 -#define SIRFSOC_CLKC_RGMII_CLK_SEL 0x00e8 -#define SIRFSOC_CLKC_RGMII_CLK_SEL_STAT 0x00ec - -#define SIRFSOC_CLKC_CPU_CLKDIV_CFG 0x00f0 -#define SIRFSOC_CLKC_CPU_CLKDIV_ENA 0x00f4 -#define SIRFSOC_CLKC_CPU_CLK_SEL 0x00f8 -#define SIRFSOC_CLKC_CPU_CLK_SEL_STAT 0x00fc - -#define SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG 0x0100 -#define SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA 0x0104 -#define SIRFSOC_CLKC_SDPHY01_CLK_SEL 0x0108 -#define SIRFSOC_CLKC_SDPHY01_CLK_SEL_STAT 0x010c - -#define SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG 0x0110 -#define SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA 0x0114 -#define SIRFSOC_CLKC_SDPHY23_CLK_SEL 0x0118 -#define SIRFSOC_CLKC_SDPHY23_CLK_SEL_STAT 0x011c - -#define SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG 0x0120 -#define SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA 0x0124 -#define SIRFSOC_CLKC_SDPHY45_CLK_SEL 0x0128 -#define SIRFSOC_CLKC_SDPHY45_CLK_SEL_STAT 0x012c - -#define SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG 0x0130 -#define SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA 0x0134 -#define SIRFSOC_CLKC_SDPHY67_CLK_SEL 0x0138 -#define SIRFSOC_CLKC_SDPHY67_CLK_SEL_STAT 0x013c - -#define SIRFSOC_CLKC_CAN_CLKDIV_CFG 0x0140 -#define SIRFSOC_CLKC_CAN_CLKDIV_ENA 0x0144 -#define SIRFSOC_CLKC_CAN_CLK_SEL 0x0148 -#define SIRFSOC_CLKC_CAN_CLK_SEL_STAT 0x014c - -#define SIRFSOC_CLKC_DEINT_CLKDIV_CFG 0x0150 -#define SIRFSOC_CLKC_DEINT_CLKDIV_ENA 0x0154 -#define SIRFSOC_CLKC_DEINT_CLK_SEL 0x0158 -#define SIRFSOC_CLKC_DEINT_CLK_SEL_STAT 0x015c - -#define SIRFSOC_CLKC_NAND_CLKDIV_CFG 0x0160 -#define SIRFSOC_CLKC_NAND_CLKDIV_ENA 0x0164 -#define SIRFSOC_CLKC_NAND_CLK_SEL 0x0168 -#define SIRFSOC_CLKC_NAND_CLK_SEL_STAT 0x016c - -#define SIRFSOC_CLKC_DISP0_CLKDIV_CFG 0x0170 -#define SIRFSOC_CLKC_DISP0_CLKDIV_ENA 0x0174 -#define SIRFSOC_CLKC_DISP0_CLK_SEL 0x0178 -#define SIRFSOC_CLKC_DISP0_CLK_SEL_STAT 0x017c - -#define SIRFSOC_CLKC_DISP1_CLKDIV_CFG 0x0180 -#define SIRFSOC_CLKC_DISP1_CLKDIV_ENA 0x0184 -#define SIRFSOC_CLKC_DISP1_CLK_SEL 0x0188 -#define SIRFSOC_CLKC_DISP1_CLK_SEL_STAT 0x018c - -#define SIRFSOC_CLKC_GPU_CLKDIV_CFG 0x0190 -#define SIRFSOC_CLKC_GPU_CLKDIV_ENA 0x0194 -#define SIRFSOC_CLKC_GPU_CLK_SEL 0x0198 -#define SIRFSOC_CLKC_GPU_CLK_SEL_STAT 0x019c - -#define SIRFSOC_CLKC_GNSS_CLKDIV_CFG 0x01a0 -#define SIRFSOC_CLKC_GNSS_CLKDIV_ENA 0x01a4 -#define SIRFSOC_CLKC_GNSS_CLK_SEL 0x01a8 -#define SIRFSOC_CLKC_GNSS_CLK_SEL_STAT 0x01ac - -#define SIRFSOC_CLKC_SHARED_DIVIDER_CFG0 0x01b0 -#define SIRFSOC_CLKC_SHARED_DIVIDER_CFG1 0x01b4 -#define SIRFSOC_CLKC_SHARED_DIVIDER_ENA 0x01b8 - -#define SIRFSOC_CLKC_SYS_CLK_SEL 0x01bc -#define SIRFSOC_CLKC_SYS_CLK_SEL_STAT 0x01c0 -#define SIRFSOC_CLKC_IO_CLK_SEL 0x01c4 -#define SIRFSOC_CLKC_IO_CLK_SEL_STAT 0x01c8 -#define SIRFSOC_CLKC_G2D_CLK_SEL 0x01cc -#define SIRFSOC_CLKC_G2D_CLK_SEL_STAT 0x01d0 -#define SIRFSOC_CLKC_JPENC_CLK_SEL 0x01d4 -#define SIRFSOC_CLKC_JPENC_CLK_SEL_STAT 0x01d8 -#define SIRFSOC_CLKC_VDEC_CLK_SEL 0x01dc -#define SIRFSOC_CLKC_VDEC_CLK_SEL_STAT 0x01e0 -#define SIRFSOC_CLKC_GMAC_CLK_SEL 0x01e4 -#define SIRFSOC_CLKC_GMAC_CLK_SEL_STAT 0x01e8 -#define SIRFSOC_CLKC_USB_CLK_SEL 0x01ec -#define SIRFSOC_CLKC_USB_CLK_SEL_STAT 0x01f0 -#define SIRFSOC_CLKC_KAS_CLK_SEL 0x01f4 -#define SIRFSOC_CLKC_KAS_CLK_SEL_STAT 0x01f8 -#define SIRFSOC_CLKC_SEC_CLK_SEL 0x01fc -#define SIRFSOC_CLKC_SEC_CLK_SEL_STAT 0x0200 -#define SIRFSOC_CLKC_SDR_CLK_SEL 0x0204 -#define SIRFSOC_CLKC_SDR_CLK_SEL_STAT 0x0208 -#define SIRFSOC_CLKC_VIP_CLK_SEL 0x020c -#define SIRFSOC_CLKC_VIP_CLK_SEL_STAT 0x0210 -#define SIRFSOC_CLKC_NOCD_CLK_SEL 0x0214 -#define SIRFSOC_CLKC_NOCD_CLK_SEL_STAT 0x0218 -#define SIRFSOC_CLKC_NOCR_CLK_SEL 0x021c -#define SIRFSOC_CLKC_NOCR_CLK_SEL_STAT 0x0220 -#define SIRFSOC_CLKC_TPIU_CLK_SEL 0x0224 -#define SIRFSOC_CLKC_TPIU_CLK_SEL_STAT 0x0228 - -#define SIRFSOC_CLKC_ROOT_CLK_EN0_SET 0x022c -#define SIRFSOC_CLKC_ROOT_CLK_EN0_CLR 0x0230 -#define SIRFSOC_CLKC_ROOT_CLK_EN0_STAT 0x0234 -#define SIRFSOC_CLKC_ROOT_CLK_EN1_SET 0x0238 -#define SIRFSOC_CLKC_ROOT_CLK_EN1_CLR 0x023c -#define SIRFSOC_CLKC_ROOT_CLK_EN1_STAT 0x0240 - -#define SIRFSOC_CLKC_LEAF_CLK_EN0_SET 0x0244 -#define SIRFSOC_CLKC_LEAF_CLK_EN0_CLR 0x0248 -#define SIRFSOC_CLKC_LEAF_CLK_EN0_STAT 0x024c - -#define SIRFSOC_CLKC_RSTC_A7_SW_RST 0x0308 - -#define SIRFSOC_CLKC_LEAF_CLK_EN1_SET 0x04a0 -#define SIRFSOC_CLKC_LEAF_CLK_EN2_SET 0x04b8 -#define SIRFSOC_CLKC_LEAF_CLK_EN3_SET 0x04d0 -#define SIRFSOC_CLKC_LEAF_CLK_EN4_SET 0x04e8 -#define SIRFSOC_CLKC_LEAF_CLK_EN5_SET 0x0500 -#define SIRFSOC_CLKC_LEAF_CLK_EN6_SET 0x0518 -#define SIRFSOC_CLKC_LEAF_CLK_EN7_SET 0x0530 -#define SIRFSOC_CLKC_LEAF_CLK_EN8_SET 0x0548 - -#define SIRFSOC_NOC_CLK_IDLEREQ_SET 0x02D0 -#define SIRFSOC_NOC_CLK_IDLEREQ_CLR 0x02D4 -#define SIRFSOC_NOC_CLK_SLVRDY_SET 0x02E8 -#define SIRFSOC_NOC_CLK_SLVRDY_CLR 0x02EC -#define SIRFSOC_NOC_CLK_IDLE_STATUS 0x02F4 - -struct clk_pll { - struct clk_hw hw; - u16 regofs; /* register offset */ -}; -#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) - -struct clk_dto { - struct clk_hw hw; - u16 inc_offset; /* dto increment offset */ - u16 src_offset; /* dto src offset */ -}; -#define to_dtoclk(_hw) container_of(_hw, struct clk_dto, hw) - -enum clk_unit_type { - CLK_UNIT_NOC_OTHER, - CLK_UNIT_NOC_CLOCK, - CLK_UNIT_NOC_SOCKET, -}; - -struct clk_unit { - struct clk_hw hw; - u16 regofs; - u16 bit; - u32 type; - u8 idle_bit; - spinlock_t *lock; -}; -#define to_unitclk(_hw) container_of(_hw, struct clk_unit, hw) - -struct atlas7_div_init_data { - const char *div_name; - const char *parent_name; - const char *gate_name; - unsigned long flags; - u8 divider_flags; - u8 gate_flags; - u32 div_offset; - u8 shift; - u8 width; - u32 gate_offset; - u8 gate_bit; - spinlock_t *lock; -}; - -struct atlas7_mux_init_data { - const char *mux_name; - const char * const *parent_names; - u8 parent_num; - unsigned long flags; - u8 mux_flags; - u32 mux_offset; - u8 shift; - u8 width; -}; - -struct atlas7_unit_init_data { - u32 index; - const char *unit_name; - const char *parent_name; - unsigned long flags; - u32 regofs; - u8 bit; - u32 type; - u8 idle_bit; - spinlock_t *lock; -}; - -struct atlas7_reset_desc { - const char *name; - u32 clk_ofs; - u8 clk_bit; - u32 rst_ofs; - u8 rst_bit; - spinlock_t *lock; -}; - -static void __iomem *sirfsoc_clk_vbase; -static struct clk_onecell_data clk_data; - -static const struct clk_div_table pll_div_table[] = { - { .val = 0, .div = 1 }, - { .val = 1, .div = 2 }, - { .val = 2, .div = 4 }, - { .val = 3, .div = 8 }, - { .val = 4, .div = 16 }, - { .val = 5, .div = 32 }, -}; - -static DEFINE_SPINLOCK(cpupll_ctrl1_lock); -static DEFINE_SPINLOCK(mempll_ctrl1_lock); -static DEFINE_SPINLOCK(sys0pll_ctrl1_lock); -static DEFINE_SPINLOCK(sys1pll_ctrl1_lock); -static DEFINE_SPINLOCK(sys2pll_ctrl1_lock); -static DEFINE_SPINLOCK(sys3pll_ctrl1_lock); -static DEFINE_SPINLOCK(usbphy_div_lock); -static DEFINE_SPINLOCK(btss_div_lock); -static DEFINE_SPINLOCK(rgmii_div_lock); -static DEFINE_SPINLOCK(cpu_div_lock); -static DEFINE_SPINLOCK(sdphy01_div_lock); -static DEFINE_SPINLOCK(sdphy23_div_lock); -static DEFINE_SPINLOCK(sdphy45_div_lock); -static DEFINE_SPINLOCK(sdphy67_div_lock); -static DEFINE_SPINLOCK(can_div_lock); -static DEFINE_SPINLOCK(deint_div_lock); -static DEFINE_SPINLOCK(nand_div_lock); -static DEFINE_SPINLOCK(disp0_div_lock); -static DEFINE_SPINLOCK(disp1_div_lock); -static DEFINE_SPINLOCK(gpu_div_lock); -static DEFINE_SPINLOCK(gnss_div_lock); -/* gate register shared */ -static DEFINE_SPINLOCK(share_div_lock); -static DEFINE_SPINLOCK(root0_gate_lock); -static DEFINE_SPINLOCK(root1_gate_lock); -static DEFINE_SPINLOCK(leaf0_gate_lock); -static DEFINE_SPINLOCK(leaf1_gate_lock); -static DEFINE_SPINLOCK(leaf2_gate_lock); -static DEFINE_SPINLOCK(leaf3_gate_lock); -static DEFINE_SPINLOCK(leaf4_gate_lock); -static DEFINE_SPINLOCK(leaf5_gate_lock); -static DEFINE_SPINLOCK(leaf6_gate_lock); -static DEFINE_SPINLOCK(leaf7_gate_lock); -static DEFINE_SPINLOCK(leaf8_gate_lock); - -static inline unsigned long clkc_readl(unsigned reg) -{ - return readl(sirfsoc_clk_vbase + reg); -} - -static inline void clkc_writel(u32 val, unsigned reg) -{ - writel(val, sirfsoc_clk_vbase + reg); -} - -/* -* ABPLL -* integer mode: Fvco = Fin * 2 * NF / NR -* Spread Spectrum mode: Fvco = Fin * SSN / NR -* SSN = 2^24 / (256 * ((ssdiv >> ssdepth) << ssdepth) + (ssmod << ssdepth)) -*/ -static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - unsigned long fin = parent_rate; - struct clk_pll *clk = to_pllclk(hw); - u64 rate; - u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 - - SIRFSOC_CLKC_MEMPLL_AB_FREQ); - u32 regfreq = clkc_readl(clk->regofs); - u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC - - SIRFSOC_CLKC_MEMPLL_AB_FREQ); - u32 nr = (regfreq >> 16 & (BIT(3) - 1)) + 1; - u32 nf = (regfreq & (BIT(9) - 1)) + 1; - u32 ssdiv = regssc >> 8 & (BIT(12) - 1); - u32 ssdepth = regssc >> 20 & (BIT(2) - 1); - u32 ssmod = regssc & (BIT(8) - 1); - - if (regctrl0 & SIRFSOC_ABPLL_CTRL0_BYPASS) - return fin; - - if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) { - rate = fin; - rate *= 1 << 24; - do_div(rate, nr); - do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth) - + (ssmod << ssdepth))); - } else { - rate = 2 * fin; - rate *= nf; - do_div(rate, nr); - } - return rate; -} - -static const struct clk_ops ab_pll_ops = { - .recalc_rate = pll_clk_recalc_rate, -}; - -static const char * const pll_clk_parents[] = { - "xin", -}; - -static const struct clk_init_data clk_cpupll_init = { - .name = "cpupll_vco", - .ops = &ab_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_pll clk_cpupll = { - .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ, - .hw = { - .init = &clk_cpupll_init, - }, -}; - -static const struct clk_init_data clk_mempll_init = { - .name = "mempll_vco", - .ops = &ab_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_pll clk_mempll = { - .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ, - .hw = { - .init = &clk_mempll_init, - }, -}; - -static const struct clk_init_data clk_sys0pll_init = { - .name = "sys0pll_vco", - .ops = &ab_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_pll clk_sys0pll = { - .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ, - .hw = { - .init = &clk_sys0pll_init, - }, -}; - -static const struct clk_init_data clk_sys1pll_init = { - .name = "sys1pll_vco", - .ops = &ab_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_pll clk_sys1pll = { - .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ, - .hw = { - .init = &clk_sys1pll_init, - }, -}; - -static const struct clk_init_data clk_sys2pll_init = { - .name = "sys2pll_vco", - .ops = &ab_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_pll clk_sys2pll = { - .regofs = SIRFSOC_CLKC_SYS2PLL_AB_FREQ, - .hw = { - .init = &clk_sys2pll_init, - }, -}; - -static const struct clk_init_data clk_sys3pll_init = { - .name = "sys3pll_vco", - .ops = &ab_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_pll clk_sys3pll = { - .regofs = SIRFSOC_CLKC_SYS3PLL_AB_FREQ, - .hw = { - .init = &clk_sys3pll_init, - }, -}; - -/* - * DTO in clkc, default enable double resolution mode - * double resolution mode:fout = fin * finc / 2^29 - * normal mode:fout = fin * finc / 2^28 - */ -#define DTO_RESL_DOUBLE (1ULL << 29) -#define DTO_RESL_NORMAL (1ULL << 28) - -static int dto_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_dto *clk = to_dtoclk(hw); - int reg; - - reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; - - return !!(clkc_readl(reg) & BIT(0)); -} - -static int dto_clk_enable(struct clk_hw *hw) -{ - u32 val, reg; - struct clk_dto *clk = to_dtoclk(hw); - - reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; - - val = clkc_readl(reg) | BIT(0); - clkc_writel(val, reg); - return 0; -} - -static void dto_clk_disable(struct clk_hw *hw) -{ - u32 val, reg; - struct clk_dto *clk = to_dtoclk(hw); - - reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; - - val = clkc_readl(reg) & ~BIT(0); - clkc_writel(val, reg); -} - -static unsigned long dto_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - u64 rate = parent_rate; - struct clk_dto *clk = to_dtoclk(hw); - u32 finc = clkc_readl(clk->inc_offset); - u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); - - rate *= finc; - if (droff & BIT(0)) - /* Double resolution off */ - do_div(rate, DTO_RESL_NORMAL); - else - do_div(rate, DTO_RESL_DOUBLE); - - return rate; -} - -static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - u64 dividend = rate * DTO_RESL_DOUBLE; - - do_div(dividend, *parent_rate); - dividend *= *parent_rate; - do_div(dividend, DTO_RESL_DOUBLE); - - return dividend; -} - -static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - u64 dividend = rate * DTO_RESL_DOUBLE; - struct clk_dto *clk = to_dtoclk(hw); - - do_div(dividend, parent_rate); - clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); - clkc_writel(dividend, clk->inc_offset); - - return 0; -} - -static u8 dto_clk_get_parent(struct clk_hw *hw) -{ - struct clk_dto *clk = to_dtoclk(hw); - - return clkc_readl(clk->src_offset); -} - -/* - * dto need CLK_SET_PARENT_GATE - */ -static int dto_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_dto *clk = to_dtoclk(hw); - - clkc_writel(index, clk->src_offset); - return 0; -} - -static const struct clk_ops dto_ops = { - .is_enabled = dto_clk_is_enabled, - .enable = dto_clk_enable, - .disable = dto_clk_disable, - .recalc_rate = dto_clk_recalc_rate, - .round_rate = dto_clk_round_rate, - .set_rate = dto_clk_set_rate, - .get_parent = dto_clk_get_parent, - .set_parent = dto_clk_set_parent, -}; - -/* dto parent clock as syspllvco/clk1 */ -static const char * const audiodto_clk_parents[] = { - "sys0pll_clk1", - "sys1pll_clk1", - "sys3pll_clk1", -}; - -static const struct clk_init_data clk_audiodto_init = { - .name = "audio_dto", - .ops = &dto_ops, - .parent_names = audiodto_clk_parents, - .num_parents = ARRAY_SIZE(audiodto_clk_parents), -}; - -static struct clk_dto clk_audio_dto = { - .inc_offset = SIRFSOC_CLKC_AUDIO_DTO_INC, - .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC, - .hw = { - .init = &clk_audiodto_init, - }, -}; - -static const char * const disp0dto_clk_parents[] = { - "sys0pll_clk1", - "sys1pll_clk1", - "sys3pll_clk1", -}; - -static const struct clk_init_data clk_disp0dto_init = { - .name = "disp0_dto", - .ops = &dto_ops, - .parent_names = disp0dto_clk_parents, - .num_parents = ARRAY_SIZE(disp0dto_clk_parents), -}; - -static struct clk_dto clk_disp0_dto = { - .inc_offset = SIRFSOC_CLKC_DISP0_DTO_INC, - .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC, - .hw = { - .init = &clk_disp0dto_init, - }, -}; - -static const char * const disp1dto_clk_parents[] = { - "sys0pll_clk1", - "sys1pll_clk1", - "sys3pll_clk1", -}; - -static const struct clk_init_data clk_disp1dto_init = { - .name = "disp1_dto", - .ops = &dto_ops, - .parent_names = disp1dto_clk_parents, - .num_parents = ARRAY_SIZE(disp1dto_clk_parents), -}; - -static struct clk_dto clk_disp1_dto = { - .inc_offset = SIRFSOC_CLKC_DISP1_DTO_INC, - .src_offset = SIRFSOC_CLKC_DISP1_DTO_SRC, - .hw = { - .init = &clk_disp1dto_init, - }, -}; - -static struct atlas7_div_init_data divider_list[] __initdata = { - /* div_name, parent_name, gate_name, clk_flag, divider_flag, gate_flag, div_offset, shift, wdith, gate_offset, bit_enable, lock */ - { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock }, - { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock }, - { "sys2pll_qa1", "sys2pll_fixdiv", "sys2pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 8, &usbphy_div_lock }, - { "sys3pll_qa1", "sys3pll_fixdiv", "sys3pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 12, &usbphy_div_lock }, - { "sys0pll_qa2", "sys0pll_fixdiv", "sys0pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 0, &btss_div_lock }, - { "sys1pll_qa2", "sys1pll_fixdiv", "sys1pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 4, &btss_div_lock }, - { "sys2pll_qa2", "sys2pll_fixdiv", "sys2pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 8, &btss_div_lock }, - { "sys3pll_qa2", "sys3pll_fixdiv", "sys3pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 12, &btss_div_lock }, - { "sys0pll_qa3", "sys0pll_fixdiv", "sys0pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 0, &rgmii_div_lock }, - { "sys1pll_qa3", "sys1pll_fixdiv", "sys1pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 4, &rgmii_div_lock }, - { "sys2pll_qa3", "sys2pll_fixdiv", "sys2pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 8, &rgmii_div_lock }, - { "sys3pll_qa3", "sys3pll_fixdiv", "sys3pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 12, &rgmii_div_lock }, - { "sys0pll_qa4", "sys0pll_fixdiv", "sys0pll_a4", 0, 0, 0, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 0, &cpu_div_lock }, - { "sys1pll_qa4", "sys1pll_fixdiv", "sys1pll_a4", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 4, &cpu_div_lock }, - { "sys0pll_qa5", "sys0pll_fixdiv", "sys0pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 0, &sdphy01_div_lock }, - { "sys1pll_qa5", "sys1pll_fixdiv", "sys1pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 4, &sdphy01_div_lock }, - { "sys2pll_qa5", "sys2pll_fixdiv", "sys2pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 8, &sdphy01_div_lock }, - { "sys3pll_qa5", "sys3pll_fixdiv", "sys3pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 12, &sdphy01_div_lock }, - { "sys0pll_qa6", "sys0pll_fixdiv", "sys0pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 0, &sdphy23_div_lock }, - { "sys1pll_qa6", "sys1pll_fixdiv", "sys1pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 4, &sdphy23_div_lock }, - { "sys2pll_qa6", "sys2pll_fixdiv", "sys2pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 8, &sdphy23_div_lock }, - { "sys3pll_qa6", "sys3pll_fixdiv", "sys3pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 12, &sdphy23_div_lock }, - { "sys0pll_qa7", "sys0pll_fixdiv", "sys0pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 0, &sdphy45_div_lock }, - { "sys1pll_qa7", "sys1pll_fixdiv", "sys1pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 4, &sdphy45_div_lock }, - { "sys2pll_qa7", "sys2pll_fixdiv", "sys2pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 8, &sdphy45_div_lock }, - { "sys3pll_qa7", "sys3pll_fixdiv", "sys3pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 12, &sdphy45_div_lock }, - { "sys0pll_qa8", "sys0pll_fixdiv", "sys0pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 0, &sdphy67_div_lock }, - { "sys1pll_qa8", "sys1pll_fixdiv", "sys1pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 4, &sdphy67_div_lock }, - { "sys2pll_qa8", "sys2pll_fixdiv", "sys2pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 8, &sdphy67_div_lock }, - { "sys3pll_qa8", "sys3pll_fixdiv", "sys3pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 12, &sdphy67_div_lock }, - { "sys0pll_qa9", "sys0pll_fixdiv", "sys0pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 0, &can_div_lock }, - { "sys1pll_qa9", "sys1pll_fixdiv", "sys1pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 4, &can_div_lock }, - { "sys2pll_qa9", "sys2pll_fixdiv", "sys2pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 8, &can_div_lock }, - { "sys3pll_qa9", "sys3pll_fixdiv", "sys3pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 12, &can_div_lock }, - { "sys0pll_qa10", "sys0pll_fixdiv", "sys0pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 0, &deint_div_lock }, - { "sys1pll_qa10", "sys1pll_fixdiv", "sys1pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 4, &deint_div_lock }, - { "sys2pll_qa10", "sys2pll_fixdiv", "sys2pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 8, &deint_div_lock }, - { "sys3pll_qa10", "sys3pll_fixdiv", "sys3pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 12, &deint_div_lock }, - { "sys0pll_qa11", "sys0pll_fixdiv", "sys0pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 0, &nand_div_lock }, - { "sys1pll_qa11", "sys1pll_fixdiv", "sys1pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 4, &nand_div_lock }, - { "sys2pll_qa11", "sys2pll_fixdiv", "sys2pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 8, &nand_div_lock }, - { "sys3pll_qa11", "sys3pll_fixdiv", "sys3pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 12, &nand_div_lock }, - { "sys0pll_qa12", "sys0pll_fixdiv", "sys0pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 0, &disp0_div_lock }, - { "sys1pll_qa12", "sys1pll_fixdiv", "sys1pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 4, &disp0_div_lock }, - { "sys2pll_qa12", "sys2pll_fixdiv", "sys2pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 8, &disp0_div_lock }, - { "sys3pll_qa12", "sys3pll_fixdiv", "sys3pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 12, &disp0_div_lock }, - { "sys0pll_qa13", "sys0pll_fixdiv", "sys0pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 0, &disp1_div_lock }, - { "sys1pll_qa13", "sys1pll_fixdiv", "sys1pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 4, &disp1_div_lock }, - { "sys2pll_qa13", "sys2pll_fixdiv", "sys2pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 8, &disp1_div_lock }, - { "sys3pll_qa13", "sys3pll_fixdiv", "sys3pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 12, &disp1_div_lock }, - { "sys0pll_qa14", "sys0pll_fixdiv", "sys0pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 0, &gpu_div_lock }, - { "sys1pll_qa14", "sys1pll_fixdiv", "sys1pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 4, &gpu_div_lock }, - { "sys2pll_qa14", "sys2pll_fixdiv", "sys2pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 8, &gpu_div_lock }, - { "sys3pll_qa14", "sys3pll_fixdiv", "sys3pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 12, &gpu_div_lock }, - { "sys0pll_qa15", "sys0pll_fixdiv", "sys0pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 0, &gnss_div_lock }, - { "sys1pll_qa15", "sys1pll_fixdiv", "sys1pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 4, &gnss_div_lock }, - { "sys2pll_qa15", "sys2pll_fixdiv", "sys2pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 8, &gnss_div_lock }, - { "sys3pll_qa15", "sys3pll_fixdiv", "sys3pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 12, &gnss_div_lock }, - { "sys1pll_qa18", "sys1pll_fixdiv", "sys1pll_a18", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 24, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 12, &share_div_lock }, - { "sys1pll_qa19", "sys1pll_fixdiv", "sys1pll_a19", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 16, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 8, &share_div_lock }, - { "sys1pll_qa20", "sys1pll_fixdiv", "sys1pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 4, &share_div_lock }, - { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock }, - { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock }, - { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock }, -}; - -static const char * const i2s_clk_parents[] = { - "xin", - "xinw", - "audio_dto", - /* "pwm_i2s01" */ -}; - -static const char * const usbphy_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a1", - "sys1pll_a1", - "sys2pll_a1", - "sys3pll_a1", -}; - -static const char * const btss_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a2", - "sys1pll_a2", - "sys2pll_a2", - "sys3pll_a2", -}; - -static const char * const rgmii_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a3", - "sys1pll_a3", - "sys2pll_a3", - "sys3pll_a3", -}; - -static const char * const cpu_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a4", - "sys1pll_a4", - "cpupll_clk1", -}; - -static const char * const sdphy01_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a5", - "sys1pll_a5", - "sys2pll_a5", - "sys3pll_a5", -}; - -static const char * const sdphy23_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a6", - "sys1pll_a6", - "sys2pll_a6", - "sys3pll_a6", -}; - -static const char * const sdphy45_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a7", - "sys1pll_a7", - "sys2pll_a7", - "sys3pll_a7", -}; - -static const char * const sdphy67_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a8", - "sys1pll_a8", - "sys2pll_a8", - "sys3pll_a8", -}; - -static const char * const can_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a9", - "sys1pll_a9", - "sys2pll_a9", - "sys3pll_a9", -}; - -static const char * const deint_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a10", - "sys1pll_a10", - "sys2pll_a10", - "sys3pll_a10", -}; - -static const char * const nand_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a11", - "sys1pll_a11", - "sys2pll_a11", - "sys3pll_a11", -}; - -static const char * const disp0_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a12", - "sys1pll_a12", - "sys2pll_a12", - "sys3pll_a12", - "disp0_dto", -}; - -static const char * const disp1_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a13", - "sys1pll_a13", - "sys2pll_a13", - "sys3pll_a13", - "disp1_dto", -}; - -static const char * const gpu_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a14", - "sys1pll_a14", - "sys2pll_a14", - "sys3pll_a14", -}; - -static const char * const gnss_clk_parents[] = { - "xin", - "xinw", - "sys0pll_a15", - "sys1pll_a15", - "sys2pll_a15", - "sys3pll_a15", -}; - -static const char * const sys_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const io_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const g2d_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const jpenc_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const vdec_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const gmac_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const usb_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const kas_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const sec_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const sdr_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const vip_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const nocd_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const nocr_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static const char * const tpiu_clk_parents[] = { - "xin", - "xinw", - "sys2pll_a20", - "sys1pll_a20", - "sys1pll_a19", - "sys1pll_a18", - "sys0pll_a20", - "sys1pll_a17", -}; - -static struct atlas7_mux_init_data mux_list[] __initdata = { - /* mux_name, parent_names, parent_num, flags, mux_flags, mux_offset, shift, width */ - { "i2s_mux", i2s_clk_parents, ARRAY_SIZE(i2s_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 2 }, - { "usbphy_mux", usbphy_clk_parents, ARRAY_SIZE(usbphy_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 3 }, - { "btss_mux", btss_clk_parents, ARRAY_SIZE(btss_clk_parents), 0, 0, SIRFSOC_CLKC_BTSS_CLK_SEL, 0, 3 }, - { "rgmii_mux", rgmii_clk_parents, ARRAY_SIZE(rgmii_clk_parents), 0, 0, SIRFSOC_CLKC_RGMII_CLK_SEL, 0, 3 }, - { "cpu_mux", cpu_clk_parents, ARRAY_SIZE(cpu_clk_parents), 0, 0, SIRFSOC_CLKC_CPU_CLK_SEL, 0, 3 }, - { "sdphy01_mux", sdphy01_clk_parents, ARRAY_SIZE(sdphy01_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY01_CLK_SEL, 0, 3 }, - { "sdphy23_mux", sdphy23_clk_parents, ARRAY_SIZE(sdphy23_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY23_CLK_SEL, 0, 3 }, - { "sdphy45_mux", sdphy45_clk_parents, ARRAY_SIZE(sdphy45_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY45_CLK_SEL, 0, 3 }, - { "sdphy67_mux", sdphy67_clk_parents, ARRAY_SIZE(sdphy67_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY67_CLK_SEL, 0, 3 }, - { "can_mux", can_clk_parents, ARRAY_SIZE(can_clk_parents), 0, 0, SIRFSOC_CLKC_CAN_CLK_SEL, 0, 3 }, - { "deint_mux", deint_clk_parents, ARRAY_SIZE(deint_clk_parents), 0, 0, SIRFSOC_CLKC_DEINT_CLK_SEL, 0, 3 }, - { "nand_mux", nand_clk_parents, ARRAY_SIZE(nand_clk_parents), 0, 0, SIRFSOC_CLKC_NAND_CLK_SEL, 0, 3 }, - { "disp0_mux", disp0_clk_parents, ARRAY_SIZE(disp0_clk_parents), 0, 0, SIRFSOC_CLKC_DISP0_CLK_SEL, 0, 3 }, - { "disp1_mux", disp1_clk_parents, ARRAY_SIZE(disp1_clk_parents), 0, 0, SIRFSOC_CLKC_DISP1_CLK_SEL, 0, 3 }, - { "gpu_mux", gpu_clk_parents, ARRAY_SIZE(gpu_clk_parents), 0, 0, SIRFSOC_CLKC_GPU_CLK_SEL, 0, 3 }, - { "gnss_mux", gnss_clk_parents, ARRAY_SIZE(gnss_clk_parents), 0, 0, SIRFSOC_CLKC_GNSS_CLK_SEL, 0, 3 }, - { "sys_mux", sys_clk_parents, ARRAY_SIZE(sys_clk_parents), 0, 0, SIRFSOC_CLKC_SYS_CLK_SEL, 0, 3 }, - { "io_mux", io_clk_parents, ARRAY_SIZE(io_clk_parents), 0, 0, SIRFSOC_CLKC_IO_CLK_SEL, 0, 3 }, - { "g2d_mux", g2d_clk_parents, ARRAY_SIZE(g2d_clk_parents), 0, 0, SIRFSOC_CLKC_G2D_CLK_SEL, 0, 3 }, - { "jpenc_mux", jpenc_clk_parents, ARRAY_SIZE(jpenc_clk_parents), 0, 0, SIRFSOC_CLKC_JPENC_CLK_SEL, 0, 3 }, - { "vdec_mux", vdec_clk_parents, ARRAY_SIZE(vdec_clk_parents), 0, 0, SIRFSOC_CLKC_VDEC_CLK_SEL, 0, 3 }, - { "gmac_mux", gmac_clk_parents, ARRAY_SIZE(gmac_clk_parents), 0, 0, SIRFSOC_CLKC_GMAC_CLK_SEL, 0, 3 }, - { "usb_mux", usb_clk_parents, ARRAY_SIZE(usb_clk_parents), 0, 0, SIRFSOC_CLKC_USB_CLK_SEL, 0, 3 }, - { "kas_mux", kas_clk_parents, ARRAY_SIZE(kas_clk_parents), 0, 0, SIRFSOC_CLKC_KAS_CLK_SEL, 0, 3 }, - { "sec_mux", sec_clk_parents, ARRAY_SIZE(sec_clk_parents), 0, 0, SIRFSOC_CLKC_SEC_CLK_SEL, 0, 3 }, - { "sdr_mux", sdr_clk_parents, ARRAY_SIZE(sdr_clk_parents), 0, 0, SIRFSOC_CLKC_SDR_CLK_SEL, 0, 3 }, - { "vip_mux", vip_clk_parents, ARRAY_SIZE(vip_clk_parents), 0, 0, SIRFSOC_CLKC_VIP_CLK_SEL, 0, 3 }, - { "nocd_mux", nocd_clk_parents, ARRAY_SIZE(nocd_clk_parents), 0, 0, SIRFSOC_CLKC_NOCD_CLK_SEL, 0, 3 }, - { "nocr_mux", nocr_clk_parents, ARRAY_SIZE(nocr_clk_parents), 0, 0, SIRFSOC_CLKC_NOCR_CLK_SEL, 0, 3 }, - { "tpiu_mux", tpiu_clk_parents, ARRAY_SIZE(tpiu_clk_parents), 0, 0, SIRFSOC_CLKC_TPIU_CLK_SEL, 0, 3 }, -}; - - /* new unit should add start from the tail of list */ -static struct atlas7_unit_init_data unit_list[] __initdata = { - /* unit_name, parent_name, flags, regofs, bit, lock */ - { 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, 0, 0, &root0_gate_lock }, - { 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, 0, 0, &root0_gate_lock }, - { 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, 0, 0, &root0_gate_lock }, - { 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, 0, 0, &root0_gate_lock }, - { 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, 0, 0, &root0_gate_lock }, - { 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, 0, 0, &root0_gate_lock }, - { 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, 0, 0, &root0_gate_lock }, - { 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, 0, 0, &root0_gate_lock }, - { 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, 0, 0, &root0_gate_lock }, - { 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, 0, 0, &root0_gate_lock }, - { 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, 0, 0, &root0_gate_lock }, - { 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, 0, 0, &root0_gate_lock }, - { 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, 0, 0, &root0_gate_lock }, - { 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, 0, 0, &root0_gate_lock }, - { 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, 0, 0, &root0_gate_lock }, - { 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, 0, 0, &root0_gate_lock }, - { 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, 0, 0, &root0_gate_lock }, - { 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, 0, 0, &root0_gate_lock }, - { 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, 0, 0, &root0_gate_lock }, - { 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, 0, 0, &root0_gate_lock }, - { 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, 0, 0, &root0_gate_lock }, - { 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, 0, 0, &root0_gate_lock }, - { 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, 0, 0, &root0_gate_lock }, - { 23, "btm_btss", "btss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 0, 0, 0, &root1_gate_lock }, - { 24, "mediam_usbphy", "usbphy_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 1, 0, 0, &root1_gate_lock }, - { 25, "rtcm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 2, 0, 0, &root1_gate_lock }, - { 26, "audmscm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 3, 0, 0, &root1_gate_lock }, - { 27, "vdifm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 4, 0, 0, &root1_gate_lock }, - { 28, "gnssm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 5, 0, 0, &root1_gate_lock }, - { 29, "mediam_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 6, 0, 0, &root1_gate_lock }, - { 30, "cpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 8, 0, 0, &root1_gate_lock }, - { 31, "gpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 9, 0, 0, &root1_gate_lock }, - { 32, "audmscm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 11, 0, 0, &root1_gate_lock }, - { 33, "vdifm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 12, 0, 0, &root1_gate_lock }, - { 34, "gnssm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 13, 0, 0, &root1_gate_lock }, - { 35, "mediam_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 14, 0, 0, &root1_gate_lock }, - { 36, "ddrm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 15, 0, 0, &root1_gate_lock }, - { 37, "cpum_tpiu", "tpiu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 16, 0, 0, &root1_gate_lock }, - { 38, "gpum_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 17, 0, 0, &root1_gate_lock }, - { 39, "gnssm_rgmii", "rgmii_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 20, 0, 0, &root1_gate_lock }, - { 40, "mediam_vdec", "vdec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 21, 0, 0, &root1_gate_lock }, - { 41, "gpum_sdr", "sdr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 22, 0, 0, &root1_gate_lock }, - { 42, "vdifm_deint", "deint_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 23, 0, 0, &root1_gate_lock }, - { 43, "gnssm_can", "can_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 26, 0, 0, &root1_gate_lock }, - { 44, "mediam_usb", "usb_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 28, 0, 0, &root1_gate_lock }, - { 45, "gnssm_gmac", "gmac_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 29, 0, 0, &root1_gate_lock }, - { 46, "cvd_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 0, CLK_UNIT_NOC_CLOCK, 4, &leaf1_gate_lock }, - { 47, "timer_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 1, 0, 0, &leaf1_gate_lock }, - { 48, "pulse_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 2, 0, 0, &leaf1_gate_lock }, - { 49, "tsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 3, 0, 0, &leaf1_gate_lock }, - { 50, "tsc_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 21, 0, 0, &leaf1_gate_lock }, - { 51, "ioctop_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 4, 0, 0, &leaf1_gate_lock }, - { 52, "rsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 5, 0, 0, &leaf1_gate_lock }, - { 53, "dvm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 6, CLK_UNIT_NOC_SOCKET, 7, &leaf1_gate_lock }, - { 54, "lvds_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 7, CLK_UNIT_NOC_SOCKET, 8, &leaf1_gate_lock }, - { 55, "kas_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 8, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock }, - { 56, "ac97_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 9, 0, 0, &leaf1_gate_lock }, - { 57, "usp0_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 10, CLK_UNIT_NOC_SOCKET, 4, &leaf1_gate_lock }, - { 58, "usp1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 11, CLK_UNIT_NOC_SOCKET, 5, &leaf1_gate_lock }, - { 59, "usp2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 12, CLK_UNIT_NOC_SOCKET, 6, &leaf1_gate_lock }, - { 60, "dmac2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 13, CLK_UNIT_NOC_SOCKET, 1, &leaf1_gate_lock }, - { 61, "dmac3_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 14, CLK_UNIT_NOC_SOCKET, 2, &leaf1_gate_lock }, - { 62, "audioif_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 15, CLK_UNIT_NOC_SOCKET, 0, &leaf1_gate_lock }, - { 63, "i2s1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 17, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock }, - { 64, "thaudmscm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 22, 0, 0, &leaf1_gate_lock }, - { 65, "analogtest_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 23, 0, 0, &leaf1_gate_lock }, - { 66, "sys2pci_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 0, CLK_UNIT_NOC_CLOCK, 20, &leaf2_gate_lock }, - { 67, "pciarb_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 1, 0, 0, &leaf2_gate_lock }, - { 68, "pcicopy_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 2, 0, 0, &leaf2_gate_lock }, - { 69, "rom_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 3, 0, 0, &leaf2_gate_lock }, - { 70, "sdio23_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 4, 0, 0, &leaf2_gate_lock }, - { 71, "sdio45_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 5, 0, 0, &leaf2_gate_lock }, - { 72, "sdio67_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 6, 0, 0, &leaf2_gate_lock }, - { 73, "vip1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 7, 0, 0, &leaf2_gate_lock }, - { 74, "vip1_vip", "vdifm_vip", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 16, CLK_UNIT_NOC_CLOCK, 21, &leaf2_gate_lock }, - { 75, "sdio23_sdphy23", "vdifm_sdphy23", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 8, 0, 0, &leaf2_gate_lock }, - { 76, "sdio45_sdphy45", "vdifm_sdphy45", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 9, 0, 0, &leaf2_gate_lock }, - { 77, "sdio67_sdphy67", "vdifm_sdphy67", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 10, 0, 0, &leaf2_gate_lock }, - { 78, "vpp0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 11, CLK_UNIT_NOC_CLOCK, 22, &leaf2_gate_lock }, - { 79, "lcd0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 12, CLK_UNIT_NOC_CLOCK, 18, &leaf2_gate_lock }, - { 80, "vpp1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 13, CLK_UNIT_NOC_CLOCK, 23, &leaf2_gate_lock }, - { 81, "lcd1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 14, CLK_UNIT_NOC_CLOCK, 19, &leaf2_gate_lock }, - { 82, "dcu_deint", "vdifm_deint", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 15, CLK_UNIT_NOC_CLOCK, 17, &leaf2_gate_lock }, - { 83, "vdifm_dapa_r_nocr", "vdifm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 17, 0, 0, &leaf2_gate_lock }, - { 84, "gpio1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 18, 0, 0, &leaf2_gate_lock }, - { 85, "thvdifm_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 19, 0, 0, &leaf2_gate_lock }, - { 86, "gmac_rgmii", "gnssm_rgmii", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 0, 0, 0, &leaf3_gate_lock }, - { 87, "gmac_gmac", "gnssm_gmac", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 1, CLK_UNIT_NOC_CLOCK, 10, &leaf3_gate_lock }, - { 88, "uart1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 2, CLK_UNIT_NOC_SOCKET, 14, &leaf3_gate_lock }, - { 89, "dmac0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 3, CLK_UNIT_NOC_SOCKET, 11, &leaf3_gate_lock }, - { 90, "uart0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 4, CLK_UNIT_NOC_SOCKET, 13, &leaf3_gate_lock }, - { 91, "uart2_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 5, CLK_UNIT_NOC_SOCKET, 15, &leaf3_gate_lock }, - { 92, "uart3_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 6, CLK_UNIT_NOC_SOCKET, 16, &leaf3_gate_lock }, - { 93, "uart4_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 7, CLK_UNIT_NOC_SOCKET, 17, &leaf3_gate_lock }, - { 94, "uart5_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 8, CLK_UNIT_NOC_SOCKET, 18, &leaf3_gate_lock }, - { 95, "spi1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 9, CLK_UNIT_NOC_SOCKET, 12, &leaf3_gate_lock }, - { 96, "gnss_gnss", "gnssm_gnss", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 10, 0, 0, &leaf3_gate_lock }, - { 97, "canbus1_can", "gnssm_can", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 12, CLK_UNIT_NOC_CLOCK, 7, &leaf3_gate_lock }, - { 98, "ccsec_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 15, CLK_UNIT_NOC_CLOCK, 9, &leaf3_gate_lock }, - { 99, "ccpub_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 16, CLK_UNIT_NOC_CLOCK, 8, &leaf3_gate_lock }, - { 100, "gnssm_dapa_r_nocr", "gnssm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 13, 0, 0, &leaf3_gate_lock }, - { 101, "thgnssm_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 14, 0, 0, &leaf3_gate_lock }, - { 102, "media_vdec", "mediam_vdec", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 0, CLK_UNIT_NOC_CLOCK, 3, &leaf4_gate_lock }, - { 103, "media_jpenc", "mediam_jpenc", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 1, CLK_UNIT_NOC_CLOCK, 1, &leaf4_gate_lock }, - { 104, "g2d_g2d", "mediam_g2d", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 2, CLK_UNIT_NOC_CLOCK, 12, &leaf4_gate_lock }, - { 105, "i2c0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 3, CLK_UNIT_NOC_SOCKET, 21, &leaf4_gate_lock }, - { 106, "i2c1_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 4, CLK_UNIT_NOC_SOCKET, 20, &leaf4_gate_lock }, - { 107, "gpio0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 5, CLK_UNIT_NOC_SOCKET, 19, &leaf4_gate_lock }, - { 108, "nand_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 6, 0, 0, &leaf4_gate_lock }, - { 109, "sdio01_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 7, 0, 0, &leaf4_gate_lock }, - { 110, "sys2pci2_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 8, CLK_UNIT_NOC_CLOCK, 13, &leaf4_gate_lock }, - { 111, "sdio01_sdphy01", "mediam_sdphy01", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 9, 0, 0, &leaf4_gate_lock }, - { 112, "nand_nand", "mediam_nand", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 10, CLK_UNIT_NOC_CLOCK, 14, &leaf4_gate_lock }, - { 113, "usb0_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 11, CLK_UNIT_NOC_CLOCK, 15, &leaf4_gate_lock }, - { 114, "usb1_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 12, CLK_UNIT_NOC_CLOCK, 16, &leaf4_gate_lock }, - { 115, "usbphy0_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 13, 0, 0, &leaf4_gate_lock }, - { 116, "usbphy1_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 14, 0, 0, &leaf4_gate_lock }, - { 117, "thmediam_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 15, 0, 0, &leaf4_gate_lock }, - { 118, "memc_mem", "mempll_clk1", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 0, 0, 0, &leaf5_gate_lock }, - { 119, "dapa_mem", "mempll_clk1", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 1, 0, 0, &leaf5_gate_lock }, - { 120, "nocddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 2, 0, 0, &leaf5_gate_lock }, - { 121, "thddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 3, 0, 0, &leaf5_gate_lock }, - { 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, CLK_UNIT_NOC_SOCKET, 9, &leaf6_gate_lock }, - { 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, CLK_UNIT_NOC_SOCKET, 10, &leaf6_gate_lock }, - { 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, 0, 0, &leaf6_gate_lock }, - { 125, "coresight_tpiu", "cpum_tpiu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, 0, 0, &leaf6_gate_lock }, - { 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, CLK_UNIT_NOC_CLOCK, 0, &leaf7_gate_lock }, - { 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, CLK_UNIT_NOC_CLOCK, 11, &leaf7_gate_lock }, - { 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, 0, 0, &leaf7_gate_lock }, - { 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, 0, 0, &leaf8_gate_lock }, - { 130, "dmac4_io", "a7ca_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, 0, 0, &leaf8_gate_lock }, - { 131, "uart6_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, 0, 0, &leaf8_gate_lock }, - { 132, "usp3_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, 0, 0, &leaf8_gate_lock }, - { 133, "a7ca_io", "noc_btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, 0, 0, &leaf8_gate_lock }, - { 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, 0, 0, &leaf8_gate_lock }, - { 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, 0, 0, &leaf8_gate_lock }, - { 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, 0, 0, &root1_gate_lock }, - { 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, 0, 0, &leaf8_gate_lock }, - { 138, "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, 0, 0, &leaf0_gate_lock }, - { 139, "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, 0, 0, &leaf0_gate_lock }, - { 140, "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, 0, 0, &leaf0_gate_lock }, - { 141, "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, 0, 0, &leaf0_gate_lock }, -}; - -static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)]; - -static int unit_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_unit *clk = to_unitclk(hw); - u32 reg; - - reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; - - return !!(clkc_readl(reg) & BIT(clk->bit)); -} - -static int unit_clk_enable(struct clk_hw *hw) -{ - u32 reg; - struct clk_unit *clk = to_unitclk(hw); - unsigned long flags; - - reg = clk->regofs; - - spin_lock_irqsave(clk->lock, flags); - clkc_writel(BIT(clk->bit), reg); - if (clk->type == CLK_UNIT_NOC_CLOCK) - clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR); - else if (clk->type == CLK_UNIT_NOC_SOCKET) - clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_SET); - - spin_unlock_irqrestore(clk->lock, flags); - return 0; -} - -static void unit_clk_disable(struct clk_hw *hw) -{ - u32 reg; - u32 i = 0; - struct clk_unit *clk = to_unitclk(hw); - unsigned long flags; - - reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; - spin_lock_irqsave(clk->lock, flags); - if (clk->type == CLK_UNIT_NOC_CLOCK) { - clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_SET); - while (!(clkc_readl(SIRFSOC_NOC_CLK_IDLE_STATUS) & - BIT(clk->idle_bit)) && (i++ < 100)) { - cpu_relax(); - udelay(10); - } - - if (i == 100) { - pr_err("unit NoC Clock disconnect Error:timeout\n"); - /*once timeout, undo idlereq by CLR*/ - clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR); - goto err; - } - - } else if (clk->type == CLK_UNIT_NOC_SOCKET) - clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_CLR); - - clkc_writel(BIT(clk->bit), reg); -err: - spin_unlock_irqrestore(clk->lock, flags); -} - -static const struct clk_ops unit_clk_ops = { - .is_enabled = unit_clk_is_enabled, - .enable = unit_clk_enable, - .disable = unit_clk_disable, -}; - -static struct clk * __init -atlas7_unit_clk_register(struct device *dev, const char *name, - const char * const parent_name, unsigned long flags, - u32 regofs, u8 bit, u32 type, u8 idle_bit, spinlock_t *lock) -{ - struct clk *clk; - struct clk_unit *unit; - struct clk_init_data init; - - unit = kzalloc(sizeof(*unit), GFP_KERNEL); - if (!unit) - return ERR_PTR(-ENOMEM); - - init.name = name; - init.parent_names = &parent_name; - init.num_parents = 1; - init.ops = &unit_clk_ops; - init.flags = flags; - - unit->hw.init = &init; - unit->regofs = regofs; - unit->bit = bit; - - unit->type = type; - unit->idle_bit = idle_bit; - unit->lock = lock; - - clk = clk_register(dev, &unit->hw); - if (IS_ERR(clk)) - kfree(unit); - - return clk; -} - -static struct atlas7_reset_desc atlas7_reset_unit[] = { - { "PWM", 0x0244, 0, 0x0320, 0, &leaf0_gate_lock }, /* 0-5 */ - { "THCGUM", 0x0244, 3, 0x0320, 1, &leaf0_gate_lock }, - { "CVD", 0x04A0, 0, 0x032C, 0, &leaf1_gate_lock }, - { "TIMER", 0x04A0, 1, 0x032C, 1, &leaf1_gate_lock }, - { "PULSEC", 0x04A0, 2, 0x032C, 2, &leaf1_gate_lock }, - { "TSC", 0x04A0, 3, 0x032C, 3, &leaf1_gate_lock }, - { "IOCTOP", 0x04A0, 4, 0x032C, 4, &leaf1_gate_lock }, /* 6-10 */ - { "RSC", 0x04A0, 5, 0x032C, 5, &leaf1_gate_lock }, - { "DVM", 0x04A0, 6, 0x032C, 6, &leaf1_gate_lock }, - { "LVDS", 0x04A0, 7, 0x032C, 7, &leaf1_gate_lock }, - { "KAS", 0x04A0, 8, 0x032C, 8, &leaf1_gate_lock }, - { "AC97", 0x04A0, 9, 0x032C, 9, &leaf1_gate_lock }, /* 11-15 */ - { "USP0", 0x04A0, 10, 0x032C, 10, &leaf1_gate_lock }, - { "USP1", 0x04A0, 11, 0x032C, 11, &leaf1_gate_lock }, - { "USP2", 0x04A0, 12, 0x032C, 12, &leaf1_gate_lock }, - { "DMAC2", 0x04A0, 13, 0x032C, 13, &leaf1_gate_lock }, - { "DMAC3", 0x04A0, 14, 0x032C, 14, &leaf1_gate_lock }, /* 16-20 */ - { "AUDIO", 0x04A0, 15, 0x032C, 15, &leaf1_gate_lock }, - { "I2S1", 0x04A0, 17, 0x032C, 16, &leaf1_gate_lock }, - { "PMU_AUDIO", 0x04A0, 22, 0x032C, 17, &leaf1_gate_lock }, - { "THAUDMSCM", 0x04A0, 23, 0x032C, 18, &leaf1_gate_lock }, - { "SYS2PCI", 0x04B8, 0, 0x0338, 0, &leaf2_gate_lock }, /* 21-25 */ - { "PCIARB", 0x04B8, 1, 0x0338, 1, &leaf2_gate_lock }, - { "PCICOPY", 0x04B8, 2, 0x0338, 2, &leaf2_gate_lock }, - { "ROM", 0x04B8, 3, 0x0338, 3, &leaf2_gate_lock }, - { "SDIO23", 0x04B8, 4, 0x0338, 4, &leaf2_gate_lock }, - { "SDIO45", 0x04B8, 5, 0x0338, 5, &leaf2_gate_lock }, /* 26-30 */ - { "SDIO67", 0x04B8, 6, 0x0338, 6, &leaf2_gate_lock }, - { "VIP1", 0x04B8, 7, 0x0338, 7, &leaf2_gate_lock }, - { "VPP0", 0x04B8, 11, 0x0338, 8, &leaf2_gate_lock }, - { "LCD0", 0x04B8, 12, 0x0338, 9, &leaf2_gate_lock }, - { "VPP1", 0x04B8, 13, 0x0338, 10, &leaf2_gate_lock }, /* 31-35 */ - { "LCD1", 0x04B8, 14, 0x0338, 11, &leaf2_gate_lock }, - { "DCU", 0x04B8, 15, 0x0338, 12, &leaf2_gate_lock }, - { "GPIO", 0x04B8, 18, 0x0338, 13, &leaf2_gate_lock }, - { "DAPA_VDIFM", 0x04B8, 17, 0x0338, 15, &leaf2_gate_lock }, - { "THVDIFM", 0x04B8, 19, 0x0338, 16, &leaf2_gate_lock }, /* 36-40 */ - { "RGMII", 0x04D0, 0, 0x0344, 0, &leaf3_gate_lock }, - { "GMAC", 0x04D0, 1, 0x0344, 1, &leaf3_gate_lock }, - { "UART1", 0x04D0, 2, 0x0344, 2, &leaf3_gate_lock }, - { "DMAC0", 0x04D0, 3, 0x0344, 3, &leaf3_gate_lock }, - { "UART0", 0x04D0, 4, 0x0344, 4, &leaf3_gate_lock }, /* 41-45 */ - { "UART2", 0x04D0, 5, 0x0344, 5, &leaf3_gate_lock }, - { "UART3", 0x04D0, 6, 0x0344, 6, &leaf3_gate_lock }, - { "UART4", 0x04D0, 7, 0x0344, 7, &leaf3_gate_lock }, - { "UART5", 0x04D0, 8, 0x0344, 8, &leaf3_gate_lock }, - { "SPI1", 0x04D0, 9, 0x0344, 9, &leaf3_gate_lock }, /* 46-50 */ - { "GNSS_SYS_M0", 0x04D0, 10, 0x0344, 10, &leaf3_gate_lock }, - { "CANBUS1", 0x04D0, 12, 0x0344, 11, &leaf3_gate_lock }, - { "CCSEC", 0x04D0, 15, 0x0344, 12, &leaf3_gate_lock }, - { "CCPUB", 0x04D0, 16, 0x0344, 13, &leaf3_gate_lock }, - { "DAPA_GNSSM", 0x04D0, 13, 0x0344, 14, &leaf3_gate_lock }, /* 51-55 */ - { "THGNSSM", 0x04D0, 14, 0x0344, 15, &leaf3_gate_lock }, - { "VDEC", 0x04E8, 0, 0x0350, 0, &leaf4_gate_lock }, - { "JPENC", 0x04E8, 1, 0x0350, 1, &leaf4_gate_lock }, - { "G2D", 0x04E8, 2, 0x0350, 2, &leaf4_gate_lock }, - { "I2C0", 0x04E8, 3, 0x0350, 3, &leaf4_gate_lock }, /* 56-60 */ - { "I2C1", 0x04E8, 4, 0x0350, 4, &leaf4_gate_lock }, - { "GPIO0", 0x04E8, 5, 0x0350, 5, &leaf4_gate_lock }, - { "NAND", 0x04E8, 6, 0x0350, 6, &leaf4_gate_lock }, - { "SDIO01", 0x04E8, 7, 0x0350, 7, &leaf4_gate_lock }, - { "SYS2PCI2", 0x04E8, 8, 0x0350, 8, &leaf4_gate_lock }, /* 61-65 */ - { "USB0", 0x04E8, 11, 0x0350, 9, &leaf4_gate_lock }, - { "USB1", 0x04E8, 12, 0x0350, 10, &leaf4_gate_lock }, - { "THMEDIAM", 0x04E8, 15, 0x0350, 11, &leaf4_gate_lock }, - { "MEMC_DDRPHY", 0x0500, 0, 0x035C, 0, &leaf5_gate_lock }, - { "MEMC_UPCTL", 0x0500, 0, 0x035C, 1, &leaf5_gate_lock }, /* 66-70 */ - { "DAPA_MEM", 0x0500, 1, 0x035C, 2, &leaf5_gate_lock }, - { "MEMC_MEMDIV", 0x0500, 0, 0x035C, 3, &leaf5_gate_lock }, - { "THDDRM", 0x0500, 3, 0x035C, 4, &leaf5_gate_lock }, - { "CORESIGHT", 0x0518, 3, 0x0368, 13, &leaf6_gate_lock }, - { "THCPUM", 0x0518, 4, 0x0368, 17, &leaf6_gate_lock }, /* 71-75 */ - { "GRAPHIC", 0x0530, 0, 0x0374, 0, &leaf7_gate_lock }, - { "VSS_SDR", 0x0530, 1, 0x0374, 1, &leaf7_gate_lock }, - { "THGPUM", 0x0530, 2, 0x0374, 2, &leaf7_gate_lock }, - { "DMAC4", 0x0548, 2, 0x0380, 1, &leaf8_gate_lock }, - { "UART6", 0x0548, 3, 0x0380, 2, &leaf8_gate_lock }, /* 76- */ - { "USP3", 0x0548, 4, 0x0380, 3, &leaf8_gate_lock }, - { "THBTM", 0x0548, 5, 0x0380, 5, &leaf8_gate_lock }, - { "A7CA", 0x0548, 1, 0x0380, 0, &leaf8_gate_lock }, - { "A7CA_APB", 0x0548, 5, 0x0380, 4, &leaf8_gate_lock }, -}; - -static int atlas7_reset_module(struct reset_controller_dev *rcdev, - unsigned long reset_idx) -{ - struct atlas7_reset_desc *reset = &atlas7_reset_unit[reset_idx]; - unsigned long flags; - - /* - * HW suggest unit reset sequence: - * assert sw reset (0) - * setting sw clk_en to if the clock was disabled before reset - * delay 16 clocks - * disable clock (sw clk_en = 0) - * de-assert reset (1) - * after this sequence, restore clock or not is decided by SW - */ - - spin_lock_irqsave(reset->lock, flags); - /* clock enable or not */ - if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) { - clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4); - udelay(2); - clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4); - clkc_writel(1 << reset->rst_bit, reset->rst_ofs); - /* restore clock enable */ - clkc_writel(1 << reset->clk_bit, reset->clk_ofs); - } else { - clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4); - clkc_writel(1 << reset->clk_bit, reset->clk_ofs); - udelay(2); - clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4); - clkc_writel(1 << reset->rst_bit, reset->rst_ofs); - } - spin_unlock_irqrestore(reset->lock, flags); - - return 0; -} - -static const struct reset_control_ops atlas7_rst_ops = { - .reset = atlas7_reset_module, -}; - -static struct reset_controller_dev atlas7_rst_ctlr = { - .ops = &atlas7_rst_ops, - .owner = THIS_MODULE, - .of_reset_n_cells = 1, -}; - -static void __init atlas7_clk_init(struct device_node *np) -{ - struct clk *clk; - struct atlas7_div_init_data *div; - struct atlas7_mux_init_data *mux; - struct atlas7_unit_init_data *unit; - int i; - int ret; - - sirfsoc_clk_vbase = of_iomap(np, 0); - if (!sirfsoc_clk_vbase) - panic("unable to map clkc registers\n"); - - of_node_put(np); - - clk = clk_register(NULL, &clk_cpupll.hw); - BUG_ON(!clk); - clk = clk_register(NULL, &clk_mempll.hw); - BUG_ON(!clk); - clk = clk_register(NULL, &clk_sys0pll.hw); - BUG_ON(!clk); - clk = clk_register(NULL, &clk_sys1pll.hw); - BUG_ON(!clk); - clk = clk_register(NULL, &clk_sys2pll.hw); - BUG_ON(!clk); - clk = clk_register(NULL, &clk_sys3pll.hw); - BUG_ON(!clk); - - clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0, - pll_div_table, &cpupll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0, - pll_div_table, &cpupll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0, - pll_div_table, &cpupll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0, - pll_div_table, &mempll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0, - pll_div_table, &mempll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0, - pll_div_table, &mempll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0, - pll_div_table, &sys0pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0, - pll_div_table, &sys0pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0, - pll_div_table, &sys0pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco", - CLK_SET_RATE_PARENT, 1, 2); - - clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0, - pll_div_table, &sys1pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0, - pll_div_table, &sys1pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0, - pll_div_table, &sys1pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco", - CLK_SET_RATE_PARENT, 1, 2); - - clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0, - pll_div_table, &sys2pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0, - pll_div_table, &sys2pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0, - pll_div_table, &sys2pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco", - CLK_SET_RATE_PARENT, 1, 2); - - clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0, - pll_div_table, &sys3pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0, - pll_div_table, &sys3pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0, - sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0, - pll_div_table, &sys3pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco", - CLK_SET_RATE_PARENT, 1, 2); - - BUG_ON(!clk); - clk = clk_register_fixed_factor(NULL, "xinw_fixdiv_btslow", "xinw", - CLK_SET_RATE_PARENT, 1, 4); - - BUG_ON(!clk); - clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, - 12, 0, &cpupll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, - 13, 0, &cpupll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, - 14, 0, &cpupll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1", - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, - 12, 0, &mempll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, - 13, 0, &mempll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, - 14, 0, &mempll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, - 12, 0, &sys0pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, - 13, 0, &sys0pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, - 14, 0, &sys0pll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, - 12, 0, &sys1pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, - 13, 0, &sys1pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, - 14, 0, &sys1pll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, - 12, 0, &sys2pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, - 13, 0, &sys2pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, - 14, 0, &sys2pll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, - 12, 0, &sys3pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, - 13, 0, &sys3pll_ctrl1_lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3", - CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, - 14, 0, &sys3pll_ctrl1_lock); - BUG_ON(!clk); - - clk = clk_register(NULL, &clk_audio_dto.hw); - BUG_ON(!clk); - - clk = clk_register(NULL, &clk_disp0_dto.hw); - BUG_ON(!clk); - - clk = clk_register(NULL, &clk_disp1_dto.hw); - BUG_ON(!clk); - - for (i = 0; i < ARRAY_SIZE(divider_list); i++) { - div = ÷r_list[i]; - clk = clk_register_divider(NULL, div->div_name, - div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset, - div->shift, div->width, 0, div->lock); - BUG_ON(!clk); - clk = clk_register_gate(NULL, div->gate_name, div->div_name, - div->gate_flags, sirfsoc_clk_vbase + div->gate_offset, - div->gate_bit, 0, div->lock); - BUG_ON(!clk); - } - /* ignore selector status register check */ - for (i = 0; i < ARRAY_SIZE(mux_list); i++) { - mux = &mux_list[i]; - clk = clk_register_mux(NULL, mux->mux_name, mux->parent_names, - mux->parent_num, mux->flags, - sirfsoc_clk_vbase + mux->mux_offset, - mux->shift, mux->width, - mux->mux_flags, NULL); - atlas7_clks[ARRAY_SIZE(unit_list) + i] = clk; - BUG_ON(!clk); - } - - for (i = 0; i < ARRAY_SIZE(unit_list); i++) { - unit = &unit_list[i]; - atlas7_clks[i] = atlas7_unit_clk_register(NULL, unit->unit_name, unit->parent_name, - unit->flags, unit->regofs, unit->bit, unit->type, unit->idle_bit, unit->lock); - BUG_ON(!atlas7_clks[i]); - } - - clk_data.clks = atlas7_clks; - clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list); - - ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - BUG_ON(ret); - - atlas7_rst_ctlr.of_node = np; - atlas7_rst_ctlr.nr_resets = ARRAY_SIZE(atlas7_reset_unit); - reset_controller_register(&atlas7_rst_ctlr); -} -CLK_OF_DECLARE(atlas7_clk, "sirf,atlas7-car", atlas7_clk_init); diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c deleted file mode 100644 index dcf4e25a0216..000000000000 --- a/drivers/clk/sirf/clk-common.c +++ /dev/null @@ -1,1037 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * common clks module for all SiRF SoCs - * - * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group - * company. - */ - -#include <linux/clk.h> - -#define KHZ 1000 -#define MHZ (KHZ * KHZ) - -static void __iomem *sirfsoc_clk_vbase; -static void __iomem *sirfsoc_rsc_vbase; -static struct clk_onecell_data clk_data; - -/* - * SiRFprimaII clock controller - * - 2 oscillators: osc-26MHz, rtc-32.768KHz - * - 3 standard configurable plls: pll1, pll2 & pll3 - * - 2 exclusive plls: usb phy pll and sata phy pll - * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia, - * display and sdphy. - * Each clock domain can select its own clock source from five clock sources, - * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source - * clock of the group clock. - * - dsp domain: gps, mf - * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse - * - sys domain: security - */ - -struct clk_pll { - struct clk_hw hw; - unsigned short regofs; /* register offset */ -}; - -#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) - -struct clk_dmn { - struct clk_hw hw; - signed char enable_bit; /* enable bit: 0 ~ 63 */ - unsigned short regofs; /* register offset */ -}; - -#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw) - -struct clk_std { - struct clk_hw hw; - signed char enable_bit; /* enable bit: 0 ~ 63 */ -}; - -#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) - -static int std_clk_is_enabled(struct clk_hw *hw); -static int std_clk_enable(struct clk_hw *hw); -static void std_clk_disable(struct clk_hw *hw); - -static inline unsigned long clkc_readl(unsigned reg) -{ - return readl(sirfsoc_clk_vbase + reg); -} - -static inline void clkc_writel(u32 val, unsigned reg) -{ - writel(val, sirfsoc_clk_vbase + reg); -} - -/* - * std pll - */ - -static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - unsigned long fin = parent_rate; - struct clk_pll *clk = to_pllclk(hw); - u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - - SIRFSOC_CLKC_PLL1_CFG0; - - if (clkc_readl(regcfg2) & BIT(2)) { - /* pll bypass mode */ - return fin; - } else { - /* fout = fin * nf / nr / od */ - u32 cfg0 = clkc_readl(clk->regofs); - u32 nf = (cfg0 & (BIT(13) - 1)) + 1; - u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; - u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; - WARN_ON(fin % MHZ); - return fin / MHZ * nf / nr / od * MHZ; - } -} - -static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - unsigned long fin, nf, nr, od; - u64 dividend; - - /* - * fout = fin * nf / (nr * od); - * set od = 1, nr = fin/MHz, so fout = nf * MHz - */ - rate = rate - rate % MHZ; - - nf = rate / MHZ; - if (nf > BIT(13)) - nf = BIT(13); - if (nf < 1) - nf = 1; - - fin = *parent_rate; - - nr = fin / MHZ; - if (nr > BIT(6)) - nr = BIT(6); - od = 1; - - dividend = (u64)fin * nf; - do_div(dividend, nr * od); - - return (long)dividend; -} - -static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_pll *clk = to_pllclk(hw); - unsigned long fin, nf, nr, od, reg; - - /* - * fout = fin * nf / (nr * od); - * set od = 1, nr = fin/MHz, so fout = nf * MHz - */ - - nf = rate / MHZ; - if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) - return -EINVAL; - - fin = parent_rate; - BUG_ON(fin < MHZ); - - nr = fin / MHZ; - BUG_ON((fin % MHZ) || nr > BIT(6)); - - od = 1; - - reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); - clkc_writel(reg, clk->regofs); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; - clkc_writel((nf >> 1) - 1, reg); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; - while (!(clkc_readl(reg) & BIT(6))) - cpu_relax(); - - return 0; -} - -static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - /* - * SiRF SoC has not cpu clock control, - * So bypass to it's parent pll. - */ - struct clk_hw *parent_clk = clk_hw_get_parent(hw); - struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk); - unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk); - return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate); -} - -static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - /* - * SiRF SoC has not cpu clock control, - * So return the parent pll rate. - */ - struct clk_hw *parent_clk = clk_hw_get_parent(hw); - return clk_hw_get_rate(parent_clk); -} - -static const struct clk_ops std_pll_ops = { - .recalc_rate = pll_clk_recalc_rate, - .round_rate = pll_clk_round_rate, - .set_rate = pll_clk_set_rate, -}; - -static const char * const pll_clk_parents[] = { - "osc", -}; - -static const struct clk_init_data clk_pll1_init = { - .name = "pll1", - .ops = &std_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static const struct clk_init_data clk_pll2_init = { - .name = "pll2", - .ops = &std_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static const struct clk_init_data clk_pll3_init = { - .name = "pll3", - .ops = &std_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_pll clk_pll1 = { - .regofs = SIRFSOC_CLKC_PLL1_CFG0, - .hw = { - .init = &clk_pll1_init, - }, -}; - -static struct clk_pll clk_pll2 = { - .regofs = SIRFSOC_CLKC_PLL2_CFG0, - .hw = { - .init = &clk_pll2_init, - }, -}; - -static struct clk_pll clk_pll3 = { - .regofs = SIRFSOC_CLKC_PLL3_CFG0, - .hw = { - .init = &clk_pll3_init, - }, -}; - -/* - * usb uses specified pll - */ - -static int usb_pll_clk_enable(struct clk_hw *hw) -{ - u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); - reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); - writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); - while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) & - SIRFSOC_USBPHY_PLL_LOCK)) - cpu_relax(); - - return 0; -} - -static void usb_pll_clk_disable(struct clk_hw *clk) -{ - u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); - reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); - writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); -} - -static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); - return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; -} - -static const struct clk_ops usb_pll_ops = { - .enable = usb_pll_clk_enable, - .disable = usb_pll_clk_disable, - .recalc_rate = usb_pll_clk_recalc_rate, -}; - -static const struct clk_init_data clk_usb_pll_init = { - .name = "usb_pll", - .ops = &usb_pll_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_hw usb_pll_clk_hw = { - .init = &clk_usb_pll_init, -}; - -/* - * clock domains - cpu, mem, sys/io, dsp, gfx - */ - -static const char * const dmn_clk_parents[] = { - "rtc", - "osc", - "pll1", - "pll2", - "pll3", -}; - -static u8 dmn_clk_get_parent(struct clk_hw *hw) -{ - struct clk_dmn *clk = to_dmnclk(hw); - u32 cfg = clkc_readl(clk->regofs); - const char *name = clk_hw_get_name(hw); - - /* parent of io domain can only be pll3 */ - if (strcmp(name, "io") == 0) - return 4; - - WARN_ON((cfg & (BIT(3) - 1)) > 4); - - return cfg & (BIT(3) - 1); -} - -static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent) -{ - struct clk_dmn *clk = to_dmnclk(hw); - u32 cfg = clkc_readl(clk->regofs); - const char *name = clk_hw_get_name(hw); - - /* parent of io domain can only be pll3 */ - if (strcmp(name, "io") == 0) - return -EINVAL; - - cfg &= ~(BIT(3) - 1); - clkc_writel(cfg | parent, clk->regofs); - /* BIT(3) - switching status: 1 - busy, 0 - done */ - while (clkc_readl(clk->regofs) & BIT(3)) - cpu_relax(); - - return 0; -} - -static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - -{ - unsigned long fin = parent_rate; - struct clk_dmn *clk = to_dmnclk(hw); - - u32 cfg = clkc_readl(clk->regofs); - - if (cfg & BIT(24)) { - /* fcd bypass mode */ - return fin; - } else { - /* - * wait count: bit[19:16], hold count: bit[23:20] - */ - u32 wait = (cfg >> 16) & (BIT(4) - 1); - u32 hold = (cfg >> 20) & (BIT(4) - 1); - - return fin / (wait + hold + 2); - } -} - -static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - unsigned long fin; - unsigned ratio, wait, hold; - const char *name = clk_hw_get_name(hw); - unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4; - - fin = *parent_rate; - ratio = fin / rate; - - if (ratio < 2) - ratio = 2; - if (ratio > BIT(bits + 1)) - ratio = BIT(bits + 1); - - wait = (ratio >> 1) - 1; - hold = ratio - wait - 2; - - return fin / (wait + hold + 2); -} - -static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_dmn *clk = to_dmnclk(hw); - unsigned long fin; - unsigned ratio, wait, hold, reg; - const char *name = clk_hw_get_name(hw); - unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4; - - fin = parent_rate; - ratio = fin / rate; - - if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) - return -EINVAL; - - WARN_ON(fin % rate); - - wait = (ratio >> 1) - 1; - hold = ratio - wait - 2; - - reg = clkc_readl(clk->regofs); - reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); - reg |= (wait << 16) | (hold << 20) | BIT(25); - clkc_writel(reg, clk->regofs); - - /* waiting FCD been effective */ - while (clkc_readl(clk->regofs) & BIT(25)) - cpu_relax(); - - return 0; -} - -static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - int ret1, ret2; - struct clk *cur_parent; - - if (rate == clk_get_rate(clk_pll1.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); - return ret1; - } - - if (rate == clk_get_rate(clk_pll2.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); - return ret1; - } - - if (rate == clk_get_rate(clk_pll3.hw.clk)) { - ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); - return ret1; - } - - cur_parent = clk_get_parent(hw->clk); - - /* switch to tmp pll before setting parent clock's rate */ - if (cur_parent == clk_pll1.hw.clk) { - ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); - BUG_ON(ret1); - } - - ret2 = clk_set_rate(clk_pll1.hw.clk, rate); - - ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); - - return ret2 ? ret2 : ret1; -} - -static const struct clk_ops msi_ops = { - .set_rate = dmn_clk_set_rate, - .round_rate = dmn_clk_round_rate, - .recalc_rate = dmn_clk_recalc_rate, - .set_parent = dmn_clk_set_parent, - .get_parent = dmn_clk_get_parent, -}; - -static const struct clk_init_data clk_mem_init = { - .name = "mem", - .ops = &msi_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_mem = { - .regofs = SIRFSOC_CLKC_MEM_CFG, - .hw = { - .init = &clk_mem_init, - }, -}; - -static const struct clk_init_data clk_sys_init = { - .name = "sys", - .ops = &msi_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), - .flags = CLK_SET_RATE_GATE, -}; - -static struct clk_dmn clk_sys = { - .regofs = SIRFSOC_CLKC_SYS_CFG, - .hw = { - .init = &clk_sys_init, - }, -}; - -static const struct clk_init_data clk_io_init = { - .name = "io", - .ops = &msi_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_io = { - .regofs = SIRFSOC_CLKC_IO_CFG, - .hw = { - .init = &clk_io_init, - }, -}; - -static const struct clk_ops cpu_ops = { - .set_parent = dmn_clk_set_parent, - .get_parent = dmn_clk_get_parent, - .set_rate = cpu_clk_set_rate, - .round_rate = cpu_clk_round_rate, - .recalc_rate = cpu_clk_recalc_rate, -}; - -static const struct clk_init_data clk_cpu_init = { - .name = "cpu", - .ops = &cpu_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), - .flags = CLK_SET_RATE_PARENT, -}; - -static struct clk_dmn clk_cpu = { - .regofs = SIRFSOC_CLKC_CPU_CFG, - .hw = { - .init = &clk_cpu_init, - }, -}; - -static const struct clk_ops dmn_ops = { - .is_enabled = std_clk_is_enabled, - .enable = std_clk_enable, - .disable = std_clk_disable, - .set_rate = dmn_clk_set_rate, - .round_rate = dmn_clk_round_rate, - .recalc_rate = dmn_clk_recalc_rate, - .set_parent = dmn_clk_set_parent, - .get_parent = dmn_clk_get_parent, -}; - -/* dsp, gfx, mm, lcd and vpp domain */ - -static const struct clk_init_data clk_dsp_init = { - .name = "dsp", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_dsp = { - .regofs = SIRFSOC_CLKC_DSP_CFG, - .enable_bit = 0, - .hw = { - .init = &clk_dsp_init, - }, -}; - -static const struct clk_init_data clk_gfx_init = { - .name = "gfx", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_gfx = { - .regofs = SIRFSOC_CLKC_GFX_CFG, - .enable_bit = 8, - .hw = { - .init = &clk_gfx_init, - }, -}; - -static const struct clk_init_data clk_mm_init = { - .name = "mm", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_mm = { - .regofs = SIRFSOC_CLKC_MM_CFG, - .enable_bit = 9, - .hw = { - .init = &clk_mm_init, - }, -}; - -/* - * for atlas6, gfx2d holds the bit of prima2's clk_mm - */ -#define clk_gfx2d clk_mm - -static const struct clk_init_data clk_lcd_init = { - .name = "lcd", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_lcd = { - .regofs = SIRFSOC_CLKC_LCD_CFG, - .enable_bit = 10, - .hw = { - .init = &clk_lcd_init, - }, -}; - -static const struct clk_init_data clk_vpp_init = { - .name = "vpp", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static struct clk_dmn clk_vpp = { - .regofs = SIRFSOC_CLKC_LCD_CFG, - .enable_bit = 11, - .hw = { - .init = &clk_vpp_init, - }, -}; - -static const struct clk_init_data clk_mmc01_init = { - .name = "mmc01", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static const struct clk_init_data clk_mmc23_init = { - .name = "mmc23", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -static const struct clk_init_data clk_mmc45_init = { - .name = "mmc45", - .ops = &dmn_ops, - .parent_names = dmn_clk_parents, - .num_parents = ARRAY_SIZE(dmn_clk_parents), -}; - -/* - * peripheral controllers in io domain - */ - -static int std_clk_is_enabled(struct clk_hw *hw) -{ - u32 reg; - int bit; - struct clk_std *clk = to_stdclk(hw); - - bit = clk->enable_bit % 32; - reg = clk->enable_bit / 32; - reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); - - return !!(clkc_readl(reg) & BIT(bit)); -} - -static int std_clk_enable(struct clk_hw *hw) -{ - u32 val, reg; - int bit; - struct clk_std *clk = to_stdclk(hw); - - BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); - - bit = clk->enable_bit % 32; - reg = clk->enable_bit / 32; - reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); - - val = clkc_readl(reg) | BIT(bit); - clkc_writel(val, reg); - return 0; -} - -static void std_clk_disable(struct clk_hw *hw) -{ - u32 val, reg; - int bit; - struct clk_std *clk = to_stdclk(hw); - - BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); - - bit = clk->enable_bit % 32; - reg = clk->enable_bit / 32; - reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); - - val = clkc_readl(reg) & ~BIT(bit); - clkc_writel(val, reg); -} - -static const char * const std_clk_io_parents[] = { - "io", -}; - -static const struct clk_ops ios_ops = { - .is_enabled = std_clk_is_enabled, - .enable = std_clk_enable, - .disable = std_clk_disable, -}; - -static const struct clk_init_data clk_cphif_init = { - .name = "cphif", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_cphif = { - .enable_bit = 20, - .hw = { - .init = &clk_cphif_init, - }, -}; - -static const struct clk_init_data clk_dmac0_init = { - .name = "dmac0", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_dmac0 = { - .enable_bit = 32, - .hw = { - .init = &clk_dmac0_init, - }, -}; - -static const struct clk_init_data clk_dmac1_init = { - .name = "dmac1", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_dmac1 = { - .enable_bit = 33, - .hw = { - .init = &clk_dmac1_init, - }, -}; - -static const struct clk_init_data clk_audio_init = { - .name = "audio", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_audio = { - .enable_bit = 35, - .hw = { - .init = &clk_audio_init, - }, -}; - -static const struct clk_init_data clk_uart0_init = { - .name = "uart0", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_uart0 = { - .enable_bit = 36, - .hw = { - .init = &clk_uart0_init, - }, -}; - -static const struct clk_init_data clk_uart1_init = { - .name = "uart1", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_uart1 = { - .enable_bit = 37, - .hw = { - .init = &clk_uart1_init, - }, -}; - -static const struct clk_init_data clk_uart2_init = { - .name = "uart2", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_uart2 = { - .enable_bit = 38, - .hw = { - .init = &clk_uart2_init, - }, -}; - -static const struct clk_init_data clk_usp0_init = { - .name = "usp0", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_usp0 = { - .enable_bit = 39, - .hw = { - .init = &clk_usp0_init, - }, -}; - -static const struct clk_init_data clk_usp1_init = { - .name = "usp1", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_usp1 = { - .enable_bit = 40, - .hw = { - .init = &clk_usp1_init, - }, -}; - -static const struct clk_init_data clk_usp2_init = { - .name = "usp2", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_usp2 = { - .enable_bit = 41, - .hw = { - .init = &clk_usp2_init, - }, -}; - -static const struct clk_init_data clk_vip_init = { - .name = "vip", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_vip = { - .enable_bit = 42, - .hw = { - .init = &clk_vip_init, - }, -}; - -static const struct clk_init_data clk_spi0_init = { - .name = "spi0", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_spi0 = { - .enable_bit = 43, - .hw = { - .init = &clk_spi0_init, - }, -}; - -static const struct clk_init_data clk_spi1_init = { - .name = "spi1", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_spi1 = { - .enable_bit = 44, - .hw = { - .init = &clk_spi1_init, - }, -}; - -static const struct clk_init_data clk_tsc_init = { - .name = "tsc", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_tsc = { - .enable_bit = 45, - .hw = { - .init = &clk_tsc_init, - }, -}; - -static const struct clk_init_data clk_i2c0_init = { - .name = "i2c0", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_i2c0 = { - .enable_bit = 46, - .hw = { - .init = &clk_i2c0_init, - }, -}; - -static const struct clk_init_data clk_i2c1_init = { - .name = "i2c1", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_i2c1 = { - .enable_bit = 47, - .hw = { - .init = &clk_i2c1_init, - }, -}; - -static const struct clk_init_data clk_pwmc_init = { - .name = "pwmc", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_pwmc = { - .enable_bit = 48, - .hw = { - .init = &clk_pwmc_init, - }, -}; - -static const struct clk_init_data clk_efuse_init = { - .name = "efuse", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_efuse = { - .enable_bit = 49, - .hw = { - .init = &clk_efuse_init, - }, -}; - -static const struct clk_init_data clk_pulse_init = { - .name = "pulse", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_pulse = { - .enable_bit = 50, - .hw = { - .init = &clk_pulse_init, - }, -}; - -static const char * const std_clk_dsp_parents[] = { - "dsp", -}; - -static const struct clk_init_data clk_gps_init = { - .name = "gps", - .ops = &ios_ops, - .parent_names = std_clk_dsp_parents, - .num_parents = ARRAY_SIZE(std_clk_dsp_parents), -}; - -static struct clk_std clk_gps = { - .enable_bit = 1, - .hw = { - .init = &clk_gps_init, - }, -}; - -static const struct clk_init_data clk_mf_init = { - .name = "mf", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_mf = { - .enable_bit = 2, - .hw = { - .init = &clk_mf_init, - }, -}; - -static const char * const std_clk_sys_parents[] = { - "sys", -}; - -static const struct clk_init_data clk_security_init = { - .name = "security", - .ops = &ios_ops, - .parent_names = std_clk_sys_parents, - .num_parents = ARRAY_SIZE(std_clk_sys_parents), -}; - -static struct clk_std clk_security = { - .enable_bit = 19, - .hw = { - .init = &clk_security_init, - }, -}; - -static const char * const std_clk_usb_parents[] = { - "usb_pll", -}; - -static const struct clk_init_data clk_usb0_init = { - .name = "usb0", - .ops = &ios_ops, - .parent_names = std_clk_usb_parents, - .num_parents = ARRAY_SIZE(std_clk_usb_parents), -}; - -static struct clk_std clk_usb0 = { - .enable_bit = 16, - .hw = { - .init = &clk_usb0_init, - }, -}; - -static const struct clk_init_data clk_usb1_init = { - .name = "usb1", - .ops = &ios_ops, - .parent_names = std_clk_usb_parents, - .num_parents = ARRAY_SIZE(std_clk_usb_parents), -}; - -static struct clk_std clk_usb1 = { - .enable_bit = 17, - .hw = { - .init = &clk_usb1_init, - }, -}; diff --git a/drivers/clk/sirf/clk-prima2.c b/drivers/clk/sirf/clk-prima2.c deleted file mode 100644 index d17b345f4d2d..000000000000 --- a/drivers/clk/sirf/clk-prima2.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Clock tree for CSR SiRFprimaII - * - * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group - * company. - */ - -#include <linux/module.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <linux/syscore_ops.h> - -#include "prima2.h" -#include "clk-common.c" - -static struct clk_dmn clk_mmc01 = { - .regofs = SIRFSOC_CLKC_MMC_CFG, - .enable_bit = 59, - .hw = { - .init = &clk_mmc01_init, - }, -}; - -static struct clk_dmn clk_mmc23 = { - .regofs = SIRFSOC_CLKC_MMC_CFG, - .enable_bit = 60, - .hw = { - .init = &clk_mmc23_init, - }, -}; - -static struct clk_dmn clk_mmc45 = { - .regofs = SIRFSOC_CLKC_MMC_CFG, - .enable_bit = 61, - .hw = { - .init = &clk_mmc45_init, - }, -}; - -static const struct clk_init_data clk_nand_init = { - .name = "nand", - .ops = &ios_ops, - .parent_names = std_clk_io_parents, - .num_parents = ARRAY_SIZE(std_clk_io_parents), -}; - -static struct clk_std clk_nand = { - .enable_bit = 34, - .hw = { - .init = &clk_nand_init, - }, -}; - -enum prima2_clk_index { - /* 0 1 2 3 4 5 6 7 8 9 */ - rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, - mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0, - spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1, - usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll, - usb0, usb1, cphif, maxclk, -}; - -static __initdata struct clk_hw *prima2_clk_hw_array[maxclk] = { - NULL, /* dummy */ - NULL, - &clk_pll1.hw, - &clk_pll2.hw, - &clk_pll3.hw, - &clk_mem.hw, - &clk_sys.hw, - &clk_security.hw, - &clk_dsp.hw, - &clk_gps.hw, - &clk_mf.hw, - &clk_io.hw, - &clk_cpu.hw, - &clk_uart0.hw, - &clk_uart1.hw, - &clk_uart2.hw, - &clk_tsc.hw, - &clk_i2c0.hw, - &clk_i2c1.hw, - &clk_spi0.hw, - &clk_spi1.hw, - &clk_pwmc.hw, - &clk_efuse.hw, - &clk_pulse.hw, - &clk_dmac0.hw, - &clk_dmac1.hw, - &clk_nand.hw, - &clk_audio.hw, - &clk_usp0.hw, - &clk_usp1.hw, - &clk_usp2.hw, - &clk_vip.hw, - &clk_gfx.hw, - &clk_mm.hw, - &clk_lcd.hw, - &clk_vpp.hw, - &clk_mmc01.hw, - &clk_mmc23.hw, - &clk_mmc45.hw, - &usb_pll_clk_hw, - &clk_usb0.hw, - &clk_usb1.hw, - &clk_cphif.hw, -}; - -static struct clk *prima2_clks[maxclk]; - -static void __init prima2_clk_init(struct device_node *np) -{ - struct device_node *rscnp; - int i; - - rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc"); - sirfsoc_rsc_vbase = of_iomap(rscnp, 0); - if (!sirfsoc_rsc_vbase) - panic("unable to map rsc registers\n"); - of_node_put(rscnp); - - sirfsoc_clk_vbase = of_iomap(np, 0); - if (!sirfsoc_clk_vbase) - panic("unable to map clkc registers\n"); - - /* These are always available (RTC and 26MHz OSC)*/ - prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL, 0, 32768); - prima2_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL, 0, - 26000000); - - for (i = pll1; i < maxclk; i++) { - prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]); - BUG_ON(IS_ERR(prima2_clks[i])); - } - clk_register_clkdev(prima2_clks[cpu], NULL, "cpu"); - clk_register_clkdev(prima2_clks[io], NULL, "io"); - clk_register_clkdev(prima2_clks[mem], NULL, "mem"); - clk_register_clkdev(prima2_clks[mem], NULL, "osc"); - - clk_data.clks = prima2_clks; - clk_data.clk_num = maxclk; - - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -} -CLK_OF_DECLARE(prima2_clk, "sirf,prima2-clkc", prima2_clk_init); diff --git a/drivers/clk/sirf/prima2.h b/drivers/clk/sirf/prima2.h deleted file mode 100644 index 2fb56941795d..000000000000 --- a/drivers/clk/sirf/prima2.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define SIRFSOC_CLKC_CLK_EN0 0x0000 -#define SIRFSOC_CLKC_CLK_EN1 0x0004 -#define SIRFSOC_CLKC_REF_CFG 0x0014 -#define SIRFSOC_CLKC_CPU_CFG 0x0018 -#define SIRFSOC_CLKC_MEM_CFG 0x001c -#define SIRFSOC_CLKC_SYS_CFG 0x0020 -#define SIRFSOC_CLKC_IO_CFG 0x0024 -#define SIRFSOC_CLKC_DSP_CFG 0x0028 -#define SIRFSOC_CLKC_GFX_CFG 0x002c -#define SIRFSOC_CLKC_MM_CFG 0x0030 -#define SIRFSOC_CLKC_LCD_CFG 0x0034 -#define SIRFSOC_CLKC_MMC_CFG 0x0038 -#define SIRFSOC_CLKC_PLL1_CFG0 0x0040 -#define SIRFSOC_CLKC_PLL2_CFG0 0x0044 -#define SIRFSOC_CLKC_PLL3_CFG0 0x0048 -#define SIRFSOC_CLKC_PLL1_CFG1 0x004c -#define SIRFSOC_CLKC_PLL2_CFG1 0x0050 -#define SIRFSOC_CLKC_PLL3_CFG1 0x0054 -#define SIRFSOC_CLKC_PLL1_CFG2 0x0058 -#define SIRFSOC_CLKC_PLL2_CFG2 0x005c -#define SIRFSOC_CLKC_PLL3_CFG2 0x0060 -#define SIRFSOC_USBPHY_PLL_CTRL 0x0008 -#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1) -#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2) -#define SIRFSOC_USBPHY_PLL_LOCK BIT(3) diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile deleted file mode 100644 index f130643b695d..000000000000 --- a/drivers/clk/zte/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y := clk.o -obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o -obj-$(CONFIG_ARCH_ZX) += clk-zx296718.o diff --git a/drivers/clk/zte/clk-zx296702.c b/drivers/clk/zte/clk-zx296702.c deleted file mode 100644 index e846f2a34feb..000000000000 --- a/drivers/clk/zte/clk-zx296702.c +++ /dev/null @@ -1,741 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 Linaro Ltd. - * Copyright (C) 2014 ZTE Corporation. - */ - -#include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <dt-bindings/clock/zx296702-clock.h> -#include "clk.h" - -static DEFINE_SPINLOCK(reg_lock); - -static void __iomem *topcrm_base; -static void __iomem *lsp0crpm_base; -static void __iomem *lsp1crpm_base; - -static struct clk *topclk[ZX296702_TOPCLK_END]; -static struct clk *lsp0clk[ZX296702_LSP0CLK_END]; -static struct clk *lsp1clk[ZX296702_LSP1CLK_END]; - -static struct clk_onecell_data topclk_data; -static struct clk_onecell_data lsp0clk_data; -static struct clk_onecell_data lsp1clk_data; - -#define CLK_MUX (topcrm_base + 0x04) -#define CLK_DIV (topcrm_base + 0x08) -#define CLK_EN0 (topcrm_base + 0x0c) -#define CLK_EN1 (topcrm_base + 0x10) -#define VOU_LOCAL_CLKEN (topcrm_base + 0x68) -#define VOU_LOCAL_CLKSEL (topcrm_base + 0x70) -#define VOU_LOCAL_DIV2_SET (topcrm_base + 0x74) -#define CLK_MUX1 (topcrm_base + 0x8c) - -#define CLK_SDMMC1 (lsp0crpm_base + 0x0c) -#define CLK_GPIO (lsp0crpm_base + 0x2c) -#define CLK_SPDIF0 (lsp0crpm_base + 0x10) -#define SPDIF0_DIV (lsp0crpm_base + 0x14) -#define CLK_I2S0 (lsp0crpm_base + 0x18) -#define I2S0_DIV (lsp0crpm_base + 0x1c) -#define CLK_I2S1 (lsp0crpm_base + 0x20) -#define I2S1_DIV (lsp0crpm_base + 0x24) -#define CLK_I2S2 (lsp0crpm_base + 0x34) -#define I2S2_DIV (lsp0crpm_base + 0x38) - -#define CLK_UART0 (lsp1crpm_base + 0x20) -#define CLK_UART1 (lsp1crpm_base + 0x24) -#define CLK_SDMMC0 (lsp1crpm_base + 0x2c) -#define CLK_SPDIF1 (lsp1crpm_base + 0x30) -#define SPDIF1_DIV (lsp1crpm_base + 0x34) - -static const struct zx_pll_config pll_a9_config[] = { - { .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 }, - { .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa }, - { .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 }, - { .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 }, - { .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa }, - { .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 }, -}; - -static const struct clk_div_table main_hlk_div[] = { - { .val = 1, .div = 2, }, - { .val = 3, .div = 4, }, - { /* sentinel */ } -}; - -static const struct clk_div_table a9_as1_aclk_divider[] = { - { .val = 0, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 3, .div = 4, }, - { /* sentinel */ } -}; - -static const struct clk_div_table sec_wclk_divider[] = { - { .val = 0, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 3, .div = 4, }, - { .val = 5, .div = 6, }, - { .val = 7, .div = 8, }, - { /* sentinel */ } -}; - -static const char * const matrix_aclk_sel[] = { - "pll_mm0_198M", - "osc", - "clk_148M5", - "pll_lsp_104M", -}; - -static const char * const a9_wclk_sel[] = { - "pll_a9", - "osc", - "clk_500", - "clk_250", -}; - -static const char * const a9_as1_aclk_sel[] = { - "clk_250", - "osc", - "pll_mm0_396M", - "pll_mac_333M", -}; - -static const char * const a9_trace_clkin_sel[] = { - "clk_74M25", - "pll_mm1_108M", - "clk_125", - "clk_148M5", -}; - -static const char * const decppu_aclk_sel[] = { - "clk_250", - "pll_mm0_198M", - "pll_lsp_104M", - "pll_audio_294M912", -}; - -static const char * const vou_main_wclk_sel[] = { - "clk_148M5", - "clk_74M25", - "clk_27", - "pll_mm1_54M", -}; - -static const char * const vou_scaler_wclk_sel[] = { - "clk_250", - "pll_mac_333M", - "pll_audio_294M912", - "pll_mm0_198M", -}; - -static const char * const r2d_wclk_sel[] = { - "pll_audio_294M912", - "pll_mac_333M", - "pll_a9_350M", - "pll_mm0_396M", -}; - -static const char * const ddr_wclk_sel[] = { - "pll_mac_333M", - "pll_ddr_266M", - "pll_audio_294M912", - "pll_mm0_198M", -}; - -static const char * const nand_wclk_sel[] = { - "pll_lsp_104M", - "osc", -}; - -static const char * const lsp_26_wclk_sel[] = { - "pll_lsp_26M", - "osc", -}; - -static const char * const vl0_sel[] = { - "vou_main_channel_div", - "vou_aux_channel_div", -}; - -static const char * const hdmi_sel[] = { - "vou_main_channel_wclk", - "vou_aux_channel_wclk", -}; - -static const char * const sdmmc0_wclk_sel[] = { - "lsp1_104M_wclk", - "lsp1_26M_wclk", -}; - -static const char * const sdmmc1_wclk_sel[] = { - "lsp0_104M_wclk", - "lsp0_26M_wclk", -}; - -static const char * const uart_wclk_sel[] = { - "lsp1_104M_wclk", - "lsp1_26M_wclk", -}; - -static const char * const spdif0_wclk_sel[] = { - "lsp0_104M_wclk", - "lsp0_26M_wclk", -}; - -static const char * const spdif1_wclk_sel[] = { - "lsp1_104M_wclk", - "lsp1_26M_wclk", -}; - -static const char * const i2s_wclk_sel[] = { - "lsp0_104M_wclk", - "lsp0_26M_wclk", -}; - -static inline struct clk *zx_divtbl(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width, - const struct clk_div_table *table) -{ - return clk_register_divider_table(NULL, name, parent, 0, reg, shift, - width, 0, table, ®_lock); -} - -static inline struct clk *zx_div(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width) -{ - return clk_register_divider(NULL, name, parent, 0, - reg, shift, width, 0, ®_lock); -} - -static inline struct clk *zx_mux(const char *name, const char * const *parents, - int num_parents, void __iomem *reg, u8 shift, u8 width) -{ - return clk_register_mux(NULL, name, parents, num_parents, - 0, reg, shift, width, 0, ®_lock); -} - -static inline struct clk *zx_gate(const char *name, const char *parent, - void __iomem *reg, u8 shift) -{ - return clk_register_gate(NULL, name, parent, CLK_IGNORE_UNUSED, - reg, shift, CLK_SET_RATE_PARENT, ®_lock); -} - -static void __init zx296702_top_clocks_init(struct device_node *np) -{ - struct clk **clk = topclk; - int i; - - topcrm_base = of_iomap(np, 0); - WARN_ON(!topcrm_base); - - clk[ZX296702_OSC] = - clk_register_fixed_rate(NULL, "osc", NULL, 0, 30000000); - clk[ZX296702_PLL_A9] = - clk_register_zx_pll("pll_a9", "osc", 0, topcrm_base - + 0x01c, pll_a9_config, - ARRAY_SIZE(pll_a9_config), ®_lock); - - /* TODO: pll_a9_350M look like changeble follow a9 pll */ - clk[ZX296702_PLL_A9_350M] = - clk_register_fixed_rate(NULL, "pll_a9_350M", "osc", 0, - 350000000); - clk[ZX296702_PLL_MAC_1000M] = - clk_register_fixed_rate(NULL, "pll_mac_1000M", "osc", 0, - 1000000000); - clk[ZX296702_PLL_MAC_333M] = - clk_register_fixed_rate(NULL, "pll_mac_333M", "osc", 0, - 333000000); - clk[ZX296702_PLL_MM0_1188M] = - clk_register_fixed_rate(NULL, "pll_mm0_1188M", "osc", 0, - 1188000000); - clk[ZX296702_PLL_MM0_396M] = - clk_register_fixed_rate(NULL, "pll_mm0_396M", "osc", 0, - 396000000); - clk[ZX296702_PLL_MM0_198M] = - clk_register_fixed_rate(NULL, "pll_mm0_198M", "osc", 0, - 198000000); - clk[ZX296702_PLL_MM1_108M] = - clk_register_fixed_rate(NULL, "pll_mm1_108M", "osc", 0, - 108000000); - clk[ZX296702_PLL_MM1_72M] = - clk_register_fixed_rate(NULL, "pll_mm1_72M", "osc", 0, - 72000000); - clk[ZX296702_PLL_MM1_54M] = - clk_register_fixed_rate(NULL, "pll_mm1_54M", "osc", 0, - 54000000); - clk[ZX296702_PLL_LSP_104M] = - clk_register_fixed_rate(NULL, "pll_lsp_104M", "osc", 0, - 104000000); - clk[ZX296702_PLL_LSP_26M] = - clk_register_fixed_rate(NULL, "pll_lsp_26M", "osc", 0, - 26000000); - clk[ZX296702_PLL_DDR_266M] = - clk_register_fixed_rate(NULL, "pll_ddr_266M", "osc", 0, - 266000000); - clk[ZX296702_PLL_AUDIO_294M912] = - clk_register_fixed_rate(NULL, "pll_audio_294M912", "osc", 0, - 294912000); - - /* bus clock */ - clk[ZX296702_MATRIX_ACLK] = - zx_mux("matrix_aclk", matrix_aclk_sel, - ARRAY_SIZE(matrix_aclk_sel), CLK_MUX, 2, 2); - clk[ZX296702_MAIN_HCLK] = - zx_divtbl("main_hclk", "matrix_aclk", CLK_DIV, 0, 2, - main_hlk_div); - clk[ZX296702_MAIN_PCLK] = - zx_divtbl("main_pclk", "matrix_aclk", CLK_DIV, 2, 2, - main_hlk_div); - - /* cpu clock */ - clk[ZX296702_CLK_500] = - clk_register_fixed_factor(NULL, "clk_500", "pll_mac_1000M", 0, - 1, 2); - clk[ZX296702_CLK_250] = - clk_register_fixed_factor(NULL, "clk_250", "pll_mac_1000M", 0, - 1, 4); - clk[ZX296702_CLK_125] = - clk_register_fixed_factor(NULL, "clk_125", "clk_250", 0, 1, 2); - clk[ZX296702_CLK_148M5] = - clk_register_fixed_factor(NULL, "clk_148M5", "pll_mm0_1188M", 0, - 1, 8); - clk[ZX296702_CLK_74M25] = - clk_register_fixed_factor(NULL, "clk_74M25", "pll_mm0_1188M", 0, - 1, 16); - clk[ZX296702_A9_WCLK] = - zx_mux("a9_wclk", a9_wclk_sel, ARRAY_SIZE(a9_wclk_sel), CLK_MUX, - 0, 2); - clk[ZX296702_A9_AS1_ACLK_MUX] = - zx_mux("a9_as1_aclk_mux", a9_as1_aclk_sel, - ARRAY_SIZE(a9_as1_aclk_sel), CLK_MUX, 4, 2); - clk[ZX296702_A9_TRACE_CLKIN_MUX] = - zx_mux("a9_trace_clkin_mux", a9_trace_clkin_sel, - ARRAY_SIZE(a9_trace_clkin_sel), CLK_MUX1, 0, 2); - clk[ZX296702_A9_AS1_ACLK_DIV] = - zx_divtbl("a9_as1_aclk_div", "a9_as1_aclk_mux", CLK_DIV, 4, 2, - a9_as1_aclk_divider); - - /* multi-media clock */ - clk[ZX296702_CLK_2] = - clk_register_fixed_factor(NULL, "clk_2", "pll_mm1_72M", 0, - 1, 36); - clk[ZX296702_CLK_27] = - clk_register_fixed_factor(NULL, "clk_27", "pll_mm1_54M", 0, - 1, 2); - clk[ZX296702_DECPPU_ACLK_MUX] = - zx_mux("decppu_aclk_mux", decppu_aclk_sel, - ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 6, 2); - clk[ZX296702_PPU_ACLK_MUX] = - zx_mux("ppu_aclk_mux", decppu_aclk_sel, - ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 8, 2); - clk[ZX296702_MALI400_ACLK_MUX] = - zx_mux("mali400_aclk_mux", decppu_aclk_sel, - ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 12, 2); - clk[ZX296702_VOU_ACLK_MUX] = - zx_mux("vou_aclk_mux", decppu_aclk_sel, - ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 10, 2); - clk[ZX296702_VOU_MAIN_WCLK_MUX] = - zx_mux("vou_main_wclk_mux", vou_main_wclk_sel, - ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 14, 2); - clk[ZX296702_VOU_AUX_WCLK_MUX] = - zx_mux("vou_aux_wclk_mux", vou_main_wclk_sel, - ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 16, 2); - clk[ZX296702_VOU_SCALER_WCLK_MUX] = - zx_mux("vou_scaler_wclk_mux", vou_scaler_wclk_sel, - ARRAY_SIZE(vou_scaler_wclk_sel), CLK_MUX, - 18, 2); - clk[ZX296702_R2D_ACLK_MUX] = - zx_mux("r2d_aclk_mux", decppu_aclk_sel, - ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 20, 2); - clk[ZX296702_R2D_WCLK_MUX] = - zx_mux("r2d_wclk_mux", r2d_wclk_sel, - ARRAY_SIZE(r2d_wclk_sel), CLK_MUX, 22, 2); - - /* other clock */ - clk[ZX296702_CLK_50] = - clk_register_fixed_factor(NULL, "clk_50", "pll_mac_1000M", - 0, 1, 20); - clk[ZX296702_CLK_25] = - clk_register_fixed_factor(NULL, "clk_25", "pll_mac_1000M", - 0, 1, 40); - clk[ZX296702_CLK_12] = - clk_register_fixed_factor(NULL, "clk_12", "pll_mm1_72M", - 0, 1, 6); - clk[ZX296702_CLK_16M384] = - clk_register_fixed_factor(NULL, "clk_16M384", - "pll_audio_294M912", 0, 1, 18); - clk[ZX296702_CLK_32K768] = - clk_register_fixed_factor(NULL, "clk_32K768", "clk_16M384", - 0, 1, 500); - clk[ZX296702_SEC_WCLK_DIV] = - zx_divtbl("sec_wclk_div", "pll_lsp_104M", CLK_DIV, 6, 3, - sec_wclk_divider); - clk[ZX296702_DDR_WCLK_MUX] = - zx_mux("ddr_wclk_mux", ddr_wclk_sel, - ARRAY_SIZE(ddr_wclk_sel), CLK_MUX, 24, 2); - clk[ZX296702_NAND_WCLK_MUX] = - zx_mux("nand_wclk_mux", nand_wclk_sel, - ARRAY_SIZE(nand_wclk_sel), CLK_MUX, 24, 2); - clk[ZX296702_LSP_26_WCLK_MUX] = - zx_mux("lsp_26_wclk_mux", lsp_26_wclk_sel, - ARRAY_SIZE(lsp_26_wclk_sel), CLK_MUX, 27, 1); - - /* gates */ - clk[ZX296702_A9_AS0_ACLK] = - zx_gate("a9_as0_aclk", "matrix_aclk", CLK_EN0, 0); - clk[ZX296702_A9_AS1_ACLK] = - zx_gate("a9_as1_aclk", "a9_as1_aclk_div", CLK_EN0, 1); - clk[ZX296702_A9_TRACE_CLKIN] = - zx_gate("a9_trace_clkin", "a9_trace_clkin_mux", CLK_EN0, 2); - clk[ZX296702_DECPPU_AXI_M_ACLK] = - zx_gate("decppu_axi_m_aclk", "decppu_aclk_mux", CLK_EN0, 3); - clk[ZX296702_DECPPU_AHB_S_HCLK] = - zx_gate("decppu_ahb_s_hclk", "main_hclk", CLK_EN0, 4); - clk[ZX296702_PPU_AXI_M_ACLK] = - zx_gate("ppu_axi_m_aclk", "ppu_aclk_mux", CLK_EN0, 5); - clk[ZX296702_PPU_AHB_S_HCLK] = - zx_gate("ppu_ahb_s_hclk", "main_hclk", CLK_EN0, 6); - clk[ZX296702_VOU_AXI_M_ACLK] = - zx_gate("vou_axi_m_aclk", "vou_aclk_mux", CLK_EN0, 7); - clk[ZX296702_VOU_APB_PCLK] = - zx_gate("vou_apb_pclk", "main_pclk", CLK_EN0, 8); - clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] = - zx_gate("vou_main_channel_wclk", "vou_main_wclk_mux", - CLK_EN0, 9); - clk[ZX296702_VOU_AUX_CHANNEL_WCLK] = - zx_gate("vou_aux_channel_wclk", "vou_aux_wclk_mux", - CLK_EN0, 10); - clk[ZX296702_VOU_HDMI_OSCLK_CEC] = - zx_gate("vou_hdmi_osclk_cec", "clk_2", CLK_EN0, 11); - clk[ZX296702_VOU_SCALER_WCLK] = - zx_gate("vou_scaler_wclk", "vou_scaler_wclk_mux", CLK_EN0, 12); - clk[ZX296702_MALI400_AXI_M_ACLK] = - zx_gate("mali400_axi_m_aclk", "mali400_aclk_mux", CLK_EN0, 13); - clk[ZX296702_MALI400_APB_PCLK] = - zx_gate("mali400_apb_pclk", "main_pclk", CLK_EN0, 14); - clk[ZX296702_R2D_WCLK] = - zx_gate("r2d_wclk", "r2d_wclk_mux", CLK_EN0, 15); - clk[ZX296702_R2D_AXI_M_ACLK] = - zx_gate("r2d_axi_m_aclk", "r2d_aclk_mux", CLK_EN0, 16); - clk[ZX296702_R2D_AHB_HCLK] = - zx_gate("r2d_ahb_hclk", "main_hclk", CLK_EN0, 17); - clk[ZX296702_DDR3_AXI_S0_ACLK] = - zx_gate("ddr3_axi_s0_aclk", "matrix_aclk", CLK_EN0, 18); - clk[ZX296702_DDR3_APB_PCLK] = - zx_gate("ddr3_apb_pclk", "main_pclk", CLK_EN0, 19); - clk[ZX296702_DDR3_WCLK] = - zx_gate("ddr3_wclk", "ddr_wclk_mux", CLK_EN0, 20); - clk[ZX296702_USB20_0_AHB_HCLK] = - zx_gate("usb20_0_ahb_hclk", "main_hclk", CLK_EN0, 21); - clk[ZX296702_USB20_0_EXTREFCLK] = - zx_gate("usb20_0_extrefclk", "clk_12", CLK_EN0, 22); - clk[ZX296702_USB20_1_AHB_HCLK] = - zx_gate("usb20_1_ahb_hclk", "main_hclk", CLK_EN0, 23); - clk[ZX296702_USB20_1_EXTREFCLK] = - zx_gate("usb20_1_extrefclk", "clk_12", CLK_EN0, 24); - clk[ZX296702_USB20_2_AHB_HCLK] = - zx_gate("usb20_2_ahb_hclk", "main_hclk", CLK_EN0, 25); - clk[ZX296702_USB20_2_EXTREFCLK] = - zx_gate("usb20_2_extrefclk", "clk_12", CLK_EN0, 26); - clk[ZX296702_GMAC_AXI_M_ACLK] = - zx_gate("gmac_axi_m_aclk", "matrix_aclk", CLK_EN0, 27); - clk[ZX296702_GMAC_APB_PCLK] = - zx_gate("gmac_apb_pclk", "main_pclk", CLK_EN0, 28); - clk[ZX296702_GMAC_125_CLKIN] = - zx_gate("gmac_125_clkin", "clk_125", CLK_EN0, 29); - clk[ZX296702_GMAC_RMII_CLKIN] = - zx_gate("gmac_rmii_clkin", "clk_50", CLK_EN0, 30); - clk[ZX296702_GMAC_25M_CLK] = - zx_gate("gmac_25M_clk", "clk_25", CLK_EN0, 31); - clk[ZX296702_NANDFLASH_AHB_HCLK] = - zx_gate("nandflash_ahb_hclk", "main_hclk", CLK_EN1, 0); - clk[ZX296702_NANDFLASH_WCLK] = - zx_gate("nandflash_wclk", "nand_wclk_mux", CLK_EN1, 1); - clk[ZX296702_LSP0_APB_PCLK] = - zx_gate("lsp0_apb_pclk", "main_pclk", CLK_EN1, 2); - clk[ZX296702_LSP0_AHB_HCLK] = - zx_gate("lsp0_ahb_hclk", "main_hclk", CLK_EN1, 3); - clk[ZX296702_LSP0_26M_WCLK] = - zx_gate("lsp0_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 4); - clk[ZX296702_LSP0_104M_WCLK] = - zx_gate("lsp0_104M_wclk", "pll_lsp_104M", CLK_EN1, 5); - clk[ZX296702_LSP0_16M384_WCLK] = - zx_gate("lsp0_16M384_wclk", "clk_16M384", CLK_EN1, 6); - clk[ZX296702_LSP1_APB_PCLK] = - zx_gate("lsp1_apb_pclk", "main_pclk", CLK_EN1, 7); - /* FIXME: wclk enable bit is bit8. We hack it as reserved 31 for - * UART does not work after parent clk is disabled/enabled */ - clk[ZX296702_LSP1_26M_WCLK] = - zx_gate("lsp1_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 31); - clk[ZX296702_LSP1_104M_WCLK] = - zx_gate("lsp1_104M_wclk", "pll_lsp_104M", CLK_EN1, 9); - clk[ZX296702_LSP1_32K_CLK] = - zx_gate("lsp1_32K_clk", "clk_32K768", CLK_EN1, 10); - clk[ZX296702_AON_HCLK] = - zx_gate("aon_hclk", "main_hclk", CLK_EN1, 11); - clk[ZX296702_SYS_CTRL_PCLK] = - zx_gate("sys_ctrl_pclk", "main_pclk", CLK_EN1, 12); - clk[ZX296702_DMA_PCLK] = - zx_gate("dma_pclk", "main_pclk", CLK_EN1, 13); - clk[ZX296702_DMA_ACLK] = - zx_gate("dma_aclk", "matrix_aclk", CLK_EN1, 14); - clk[ZX296702_SEC_HCLK] = - zx_gate("sec_hclk", "main_hclk", CLK_EN1, 15); - clk[ZX296702_AES_WCLK] = - zx_gate("aes_wclk", "sec_wclk_div", CLK_EN1, 16); - clk[ZX296702_DES_WCLK] = - zx_gate("des_wclk", "sec_wclk_div", CLK_EN1, 17); - clk[ZX296702_IRAM_ACLK] = - zx_gate("iram_aclk", "matrix_aclk", CLK_EN1, 18); - clk[ZX296702_IROM_ACLK] = - zx_gate("irom_aclk", "matrix_aclk", CLK_EN1, 19); - clk[ZX296702_BOOT_CTRL_HCLK] = - zx_gate("boot_ctrl_hclk", "main_hclk", CLK_EN1, 20); - clk[ZX296702_EFUSE_CLK_30] = - zx_gate("efuse_clk_30", "osc", CLK_EN1, 21); - - /* TODO: add VOU Local clocks */ - clk[ZX296702_VOU_MAIN_CHANNEL_DIV] = - zx_div("vou_main_channel_div", "vou_main_channel_wclk", - VOU_LOCAL_DIV2_SET, 1, 1); - clk[ZX296702_VOU_AUX_CHANNEL_DIV] = - zx_div("vou_aux_channel_div", "vou_aux_channel_wclk", - VOU_LOCAL_DIV2_SET, 0, 1); - clk[ZX296702_VOU_TV_ENC_HD_DIV] = - zx_div("vou_tv_enc_hd_div", "vou_tv_enc_hd_mux", - VOU_LOCAL_DIV2_SET, 3, 1); - clk[ZX296702_VOU_TV_ENC_SD_DIV] = - zx_div("vou_tv_enc_sd_div", "vou_tv_enc_sd_mux", - VOU_LOCAL_DIV2_SET, 2, 1); - clk[ZX296702_VL0_MUX] = - zx_mux("vl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel), - VOU_LOCAL_CLKSEL, 8, 1); - clk[ZX296702_VL1_MUX] = - zx_mux("vl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel), - VOU_LOCAL_CLKSEL, 9, 1); - clk[ZX296702_VL2_MUX] = - zx_mux("vl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel), - VOU_LOCAL_CLKSEL, 10, 1); - clk[ZX296702_GL0_MUX] = - zx_mux("gl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel), - VOU_LOCAL_CLKSEL, 5, 1); - clk[ZX296702_GL1_MUX] = - zx_mux("gl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel), - VOU_LOCAL_CLKSEL, 6, 1); - clk[ZX296702_GL2_MUX] = - zx_mux("gl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel), - VOU_LOCAL_CLKSEL, 7, 1); - clk[ZX296702_WB_MUX] = - zx_mux("wb_mux", vl0_sel, ARRAY_SIZE(vl0_sel), - VOU_LOCAL_CLKSEL, 11, 1); - clk[ZX296702_HDMI_MUX] = - zx_mux("hdmi_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel), - VOU_LOCAL_CLKSEL, 4, 1); - clk[ZX296702_VOU_TV_ENC_HD_MUX] = - zx_mux("vou_tv_enc_hd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel), - VOU_LOCAL_CLKSEL, 3, 1); - clk[ZX296702_VOU_TV_ENC_SD_MUX] = - zx_mux("vou_tv_enc_sd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel), - VOU_LOCAL_CLKSEL, 2, 1); - clk[ZX296702_VL0_CLK] = - zx_gate("vl0_clk", "vl0_mux", VOU_LOCAL_CLKEN, 8); - clk[ZX296702_VL1_CLK] = - zx_gate("vl1_clk", "vl1_mux", VOU_LOCAL_CLKEN, 9); - clk[ZX296702_VL2_CLK] = - zx_gate("vl2_clk", "vl2_mux", VOU_LOCAL_CLKEN, 10); - clk[ZX296702_GL0_CLK] = - zx_gate("gl0_clk", "gl0_mux", VOU_LOCAL_CLKEN, 5); - clk[ZX296702_GL1_CLK] = - zx_gate("gl1_clk", "gl1_mux", VOU_LOCAL_CLKEN, 6); - clk[ZX296702_GL2_CLK] = - zx_gate("gl2_clk", "gl2_mux", VOU_LOCAL_CLKEN, 7); - clk[ZX296702_WB_CLK] = - zx_gate("wb_clk", "wb_mux", VOU_LOCAL_CLKEN, 11); - clk[ZX296702_CL_CLK] = - zx_gate("cl_clk", "vou_main_channel_div", VOU_LOCAL_CLKEN, 12); - clk[ZX296702_MAIN_MIX_CLK] = - zx_gate("main_mix_clk", "vou_main_channel_div", - VOU_LOCAL_CLKEN, 4); - clk[ZX296702_AUX_MIX_CLK] = - zx_gate("aux_mix_clk", "vou_aux_channel_div", - VOU_LOCAL_CLKEN, 3); - clk[ZX296702_HDMI_CLK] = - zx_gate("hdmi_clk", "hdmi_mux", VOU_LOCAL_CLKEN, 2); - clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] = - zx_gate("vou_tv_enc_hd_dac_clk", "vou_tv_enc_hd_div", - VOU_LOCAL_CLKEN, 1); - clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] = - zx_gate("vou_tv_enc_sd_dac_clk", "vou_tv_enc_sd_div", - VOU_LOCAL_CLKEN, 0); - - /* CA9 PERIPHCLK = a9_wclk / 2 */ - clk[ZX296702_A9_PERIPHCLK] = - clk_register_fixed_factor(NULL, "a9_periphclk", "a9_wclk", - 0, 1, 2); - - for (i = 0; i < ARRAY_SIZE(topclk); i++) { - if (IS_ERR(clk[i])) { - pr_err("zx296702 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - return; - } - } - - topclk_data.clks = topclk; - topclk_data.clk_num = ARRAY_SIZE(topclk); - of_clk_add_provider(np, of_clk_src_onecell_get, &topclk_data); -} -CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk", - zx296702_top_clocks_init); - -static void __init zx296702_lsp0_clocks_init(struct device_node *np) -{ - struct clk **clk = lsp0clk; - int i; - - lsp0crpm_base = of_iomap(np, 0); - WARN_ON(!lsp0crpm_base); - - /* SDMMC1 */ - clk[ZX296702_SDMMC1_WCLK_MUX] = - zx_mux("sdmmc1_wclk_mux", sdmmc1_wclk_sel, - ARRAY_SIZE(sdmmc1_wclk_sel), CLK_SDMMC1, 4, 1); - clk[ZX296702_SDMMC1_WCLK_DIV] = - zx_div("sdmmc1_wclk_div", "sdmmc1_wclk_mux", CLK_SDMMC1, 12, 4); - clk[ZX296702_SDMMC1_WCLK] = - zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1); - clk[ZX296702_SDMMC1_PCLK] = - zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0); - - clk[ZX296702_GPIO_CLK] = - zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0); - - /* SPDIF */ - clk[ZX296702_SPDIF0_WCLK_MUX] = - zx_mux("spdif0_wclk_mux", spdif0_wclk_sel, - ARRAY_SIZE(spdif0_wclk_sel), CLK_SPDIF0, 4, 1); - clk[ZX296702_SPDIF0_WCLK] = - zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1); - clk[ZX296702_SPDIF0_PCLK] = - zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0); - - clk[ZX296702_SPDIF0_DIV] = - clk_register_zx_audio("spdif0_div", "spdif0_wclk", 0, - SPDIF0_DIV); - - /* I2S */ - clk[ZX296702_I2S0_WCLK_MUX] = - zx_mux("i2s0_wclk_mux", i2s_wclk_sel, - ARRAY_SIZE(i2s_wclk_sel), CLK_I2S0, 4, 1); - clk[ZX296702_I2S0_WCLK] = - zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1); - clk[ZX296702_I2S0_PCLK] = - zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0); - - clk[ZX296702_I2S0_DIV] = - clk_register_zx_audio("i2s0_div", "i2s0_wclk", 0, I2S0_DIV); - - clk[ZX296702_I2S1_WCLK_MUX] = - zx_mux("i2s1_wclk_mux", i2s_wclk_sel, - ARRAY_SIZE(i2s_wclk_sel), CLK_I2S1, 4, 1); - clk[ZX296702_I2S1_WCLK] = - zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1); - clk[ZX296702_I2S1_PCLK] = - zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0); - - clk[ZX296702_I2S1_DIV] = - clk_register_zx_audio("i2s1_div", "i2s1_wclk", 0, I2S1_DIV); - - clk[ZX296702_I2S2_WCLK_MUX] = - zx_mux("i2s2_wclk_mux", i2s_wclk_sel, - ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1); - clk[ZX296702_I2S2_WCLK] = - zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1); - clk[ZX296702_I2S2_PCLK] = - zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0); - - clk[ZX296702_I2S2_DIV] = - clk_register_zx_audio("i2s2_div", "i2s2_wclk", 0, I2S2_DIV); - - for (i = 0; i < ARRAY_SIZE(lsp0clk); i++) { - if (IS_ERR(clk[i])) { - pr_err("zx296702 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - return; - } - } - - lsp0clk_data.clks = lsp0clk; - lsp0clk_data.clk_num = ARRAY_SIZE(lsp0clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &lsp0clk_data); -} -CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk", - zx296702_lsp0_clocks_init); - -static void __init zx296702_lsp1_clocks_init(struct device_node *np) -{ - struct clk **clk = lsp1clk; - int i; - - lsp1crpm_base = of_iomap(np, 0); - WARN_ON(!lsp1crpm_base); - - /* UART0 */ - clk[ZX296702_UART0_WCLK_MUX] = - zx_mux("uart0_wclk_mux", uart_wclk_sel, - ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1); - /* FIXME: uart wclk enable bit is bit1 in. We hack it as reserved 31 for - * UART does not work after parent clk is disabled/enabled */ - clk[ZX296702_UART0_WCLK] = - zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31); - clk[ZX296702_UART0_PCLK] = - zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0); - - /* UART1 */ - clk[ZX296702_UART1_WCLK_MUX] = - zx_mux("uart1_wclk_mux", uart_wclk_sel, - ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1); - clk[ZX296702_UART1_WCLK] = - zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1); - clk[ZX296702_UART1_PCLK] = - zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0); - - /* SDMMC0 */ - clk[ZX296702_SDMMC0_WCLK_MUX] = - zx_mux("sdmmc0_wclk_mux", sdmmc0_wclk_sel, - ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1); - clk[ZX296702_SDMMC0_WCLK_DIV] = - zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4); - clk[ZX296702_SDMMC0_WCLK] = - zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1); - clk[ZX296702_SDMMC0_PCLK] = - zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0); - - clk[ZX296702_SPDIF1_WCLK_MUX] = - zx_mux("spdif1_wclk_mux", spdif1_wclk_sel, - ARRAY_SIZE(spdif1_wclk_sel), CLK_SPDIF1, 4, 1); - clk[ZX296702_SPDIF1_WCLK] = - zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1); - clk[ZX296702_SPDIF1_PCLK] = - zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0); - - clk[ZX296702_SPDIF1_DIV] = - clk_register_zx_audio("spdif1_div", "spdif1_wclk", 0, - SPDIF1_DIV); - - for (i = 0; i < ARRAY_SIZE(lsp1clk); i++) { - if (IS_ERR(clk[i])) { - pr_err("zx296702 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - return; - } - } - - lsp1clk_data.clks = lsp1clk; - lsp1clk_data.clk_num = ARRAY_SIZE(lsp1clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &lsp1clk_data); -} -CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk", - zx296702_lsp1_clocks_init); diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c deleted file mode 100644 index dd7045bc48c1..000000000000 --- a/drivers/clk/zte/clk-zx296718.c +++ /dev/null @@ -1,1074 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 - 2016 ZTE Corporation. - * Copyright (C) 2016 Linaro Ltd. - */ -#include <linux/clk-provider.h> -#include <linux/device.h> -#include <linux/kernel.h> -#include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> - -#include <dt-bindings/clock/zx296718-clock.h> -#include "clk.h" - -/* TOP CRM */ -#define TOP_CLK_MUX0 0x04 -#define TOP_CLK_MUX1 0x08 -#define TOP_CLK_MUX2 0x0c -#define TOP_CLK_MUX3 0x10 -#define TOP_CLK_MUX4 0x14 -#define TOP_CLK_MUX5 0x18 -#define TOP_CLK_MUX6 0x1c -#define TOP_CLK_MUX7 0x20 -#define TOP_CLK_MUX9 0x28 - - -#define TOP_CLK_GATE0 0x34 -#define TOP_CLK_GATE1 0x38 -#define TOP_CLK_GATE2 0x3c -#define TOP_CLK_GATE3 0x40 -#define TOP_CLK_GATE4 0x44 -#define TOP_CLK_GATE5 0x48 -#define TOP_CLK_GATE6 0x4c - -#define TOP_CLK_DIV0 0x58 - -#define PLL_CPU_REG 0x80 -#define PLL_VGA_REG 0xb0 -#define PLL_DDR_REG 0xa0 - -/* LSP0 CRM */ -#define LSP0_TIMER3_CLK 0x4 -#define LSP0_TIMER4_CLK 0x8 -#define LSP0_TIMER5_CLK 0xc -#define LSP0_UART3_CLK 0x10 -#define LSP0_UART1_CLK 0x14 -#define LSP0_UART2_CLK 0x18 -#define LSP0_SPIFC0_CLK 0x1c -#define LSP0_I2C4_CLK 0x20 -#define LSP0_I2C5_CLK 0x24 -#define LSP0_SSP0_CLK 0x28 -#define LSP0_SSP1_CLK 0x2c -#define LSP0_USIM0_CLK 0x30 -#define LSP0_GPIO_CLK 0x34 -#define LSP0_I2C3_CLK 0x38 - -/* LSP1 CRM */ -#define LSP1_UART4_CLK 0x08 -#define LSP1_UART5_CLK 0x0c -#define LSP1_PWM_CLK 0x10 -#define LSP1_I2C2_CLK 0x14 -#define LSP1_SSP2_CLK 0x1c -#define LSP1_SSP3_CLK 0x20 -#define LSP1_SSP4_CLK 0x24 -#define LSP1_USIM1_CLK 0x28 - -/* audio lsp */ -#define AUDIO_I2S0_DIV_CFG1 0x10 -#define AUDIO_I2S0_DIV_CFG2 0x14 -#define AUDIO_I2S0_CLK 0x18 -#define AUDIO_I2S1_DIV_CFG1 0x20 -#define AUDIO_I2S1_DIV_CFG2 0x24 -#define AUDIO_I2S1_CLK 0x28 -#define AUDIO_I2S2_DIV_CFG1 0x30 -#define AUDIO_I2S2_DIV_CFG2 0x34 -#define AUDIO_I2S2_CLK 0x38 -#define AUDIO_I2S3_DIV_CFG1 0x40 -#define AUDIO_I2S3_DIV_CFG2 0x44 -#define AUDIO_I2S3_CLK 0x48 -#define AUDIO_I2C0_CLK 0x50 -#define AUDIO_SPDIF0_DIV_CFG1 0x60 -#define AUDIO_SPDIF0_DIV_CFG2 0x64 -#define AUDIO_SPDIF0_CLK 0x68 -#define AUDIO_SPDIF1_DIV_CFG1 0x70 -#define AUDIO_SPDIF1_DIV_CFG2 0x74 -#define AUDIO_SPDIF1_CLK 0x78 -#define AUDIO_TIMER_CLK 0x80 -#define AUDIO_TDM_CLK 0x90 -#define AUDIO_TS_CLK 0xa0 - -static DEFINE_SPINLOCK(clk_lock); - -static const struct zx_pll_config pll_cpu_table[] = { - PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa), - PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa), - PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa), - PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa), -}; - -static const struct zx_pll_config pll_vga_table[] = { - PLL_RATE(36000000, 0x00102464, 0x04000000), /* 800x600@56 */ - PLL_RATE(40000000, 0x00102864, 0x04000000), /* 800x600@60 */ - PLL_RATE(49500000, 0x00103164, 0x04800000), /* 800x600@75 */ - PLL_RATE(50000000, 0x00103264, 0x04000000), /* 800x600@72 */ - PLL_RATE(56250000, 0x00103864, 0x04400000), /* 800x600@85 */ - PLL_RATE(65000000, 0x00104164, 0x04000000), /* 1024x768@60 */ - PLL_RATE(74375000, 0x00104a64, 0x04600000), /* 1280x720@60 */ - PLL_RATE(75000000, 0x00104b64, 0x04800000), /* 1024x768@70 */ - PLL_RATE(78750000, 0x00104e64, 0x04c00000), /* 1024x768@75 */ - PLL_RATE(85500000, 0x00105564, 0x04800000), /* 1360x768@60 */ - PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900@60 */ - PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024@60 */ - PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768@85 */ - PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024@75 */ - PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900@75 */ - PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080@60 */ - PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900@85 */ - PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024@85 */ - PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200@60 */ - PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200@60 */ -}; - -PNAME(osc) = { - "osc24m", - "osc32k", -}; - -PNAME(dbg_wclk_p) = { - "clk334m", - "clk466m", - "clk396m", - "clk250m", -}; - -PNAME(a72_coreclk_p) = { - "osc24m", - "pll_mm0_1188m", - "pll_mm1_1296m", - "clk1000m", - "clk648m", - "clk1600m", - "pll_audio_1800m", - "pll_vga_1800m", -}; - -PNAME(cpu_periclk_p) = { - "osc24m", - "clk500m", - "clk594m", - "clk466m", - "clk294m", - "clk334m", - "clk250m", - "clk125m", -}; - -PNAME(a53_coreclk_p) = { - "osc24m", - "clk1000m", - "pll_mm0_1188m", - "clk648m", - "clk500m", - "clk800m", - "clk1600m", - "pll_audio_1800m", -}; - -PNAME(sec_wclk_p) = { - "osc24m", - "clk396m", - "clk334m", - "clk297m", - "clk250m", - "clk198m", - "clk148m5", - "clk99m", -}; - -PNAME(sd_nand_wclk_p) = { - "osc24m", - "clk49m5", - "clk99m", - "clk198m", - "clk167m", - "clk148m5", - "clk125m", - "clk216m", -}; - -PNAME(emmc_wclk_p) = { - "osc24m", - "clk198m", - "clk99m", - "clk396m", - "clk334m", - "clk297m", - "clk250m", - "clk148m5", -}; - -PNAME(clk32_p) = { - "osc32k", - "clk32k768", -}; - -PNAME(usb_ref24m_p) = { - "osc32k", - "clk32k768", -}; - -PNAME(sys_noc_alck_p) = { - "osc24m", - "clk250m", - "clk198m", - "clk148m5", - "clk108m", - "clk54m", - "clk216m", - "clk240m", -}; - -PNAME(vde_aclk_p) = { - "clk334m", - "clk594m", - "clk500m", - "clk432m", - "clk480m", - "clk297m", - "clk_vga", /*600MHz*/ - "clk294m", -}; - -PNAME(vce_aclk_p) = { - "clk334m", - "clk594m", - "clk500m", - "clk432m", - "clk396m", - "clk297m", - "clk_vga", /*600MHz*/ - "clk294m", -}; - -PNAME(hde_aclk_p) = { - "clk334m", - "clk594m", - "clk500m", - "clk432m", - "clk396m", - "clk297m", - "clk_vga", /*600MHz*/ - "clk294m", -}; - -PNAME(gpu_aclk_p) = { - "clk334m", - "clk648m", - "clk594m", - "clk500m", - "clk396m", - "clk297m", - "clk_vga", /*600MHz*/ - "clk294m", -}; - -PNAME(sappu_aclk_p) = { - "clk396m", - "clk500m", - "clk250m", - "clk148m5", -}; - -PNAME(sappu_wclk_p) = { - "clk198m", - "clk396m", - "clk334m", - "clk297m", - "clk250m", - "clk148m5", - "clk125m", - "clk99m", -}; - -PNAME(vou_aclk_p) = { - "clk334m", - "clk594m", - "clk500m", - "clk432m", - "clk396m", - "clk297m", - "clk_vga", /*600MHz*/ - "clk294m", -}; - -PNAME(vou_main_wclk_p) = { - "clk108m", - "clk594m", - "clk297m", - "clk148m5", - "clk74m25", - "clk54m", - "clk27m", - "clk_vga", -}; - -PNAME(vou_aux_wclk_p) = { - "clk108m", - "clk148m5", - "clk74m25", - "clk54m", - "clk27m", - "clk_vga", - "clk54m_mm0", - "clk" -}; - -PNAME(vou_ppu_wclk_p) = { - "clk334m", - "clk432m", - "clk396m", - "clk297m", - "clk250m", - "clk125m", - "clk198m", - "clk99m", -}; - -PNAME(vga_i2c_wclk_p) = { - "osc24m", - "clk99m", -}; - -PNAME(viu_m0_aclk_p) = { - "clk334m", - "clk432m", - "clk396m", - "clk297m", - "clk250m", - "clk125m", - "clk198m", - "osc24m", -}; - -PNAME(viu_m1_aclk_p) = { - "clk198m", - "clk250m", - "clk297m", - "clk125m", - "clk396m", - "clk334m", - "clk148m5", - "osc24m", -}; - -PNAME(viu_clk_p) = { - "clk198m", - "clk334m", - "clk297m", - "clk250m", - "clk396m", - "clk125m", - "clk99m", - "clk148m5", -}; - -PNAME(viu_jpeg_clk_p) = { - "clk334m", - "clk480m", - "clk432m", - "clk396m", - "clk297m", - "clk250m", - "clk125m", - "clk198m", -}; - -PNAME(ts_sys_clk_p) = { - "clk192m", - "clk167m", - "clk125m", - "clk99m", -}; - -PNAME(wdt_ares_p) = { - "osc24m", - "clk32k" -}; - -static struct clk_zx_pll zx296718_pll_clk[] = { - ZX296718_PLL("pll_cpu", "osc24m", PLL_CPU_REG, pll_cpu_table), - ZX296718_PLL("pll_vga", "osc24m", PLL_VGA_REG, pll_vga_table), -}; - -static struct zx_clk_fixed_factor top_ffactor_clk[] = { - FFACTOR(0, "clk4m", "osc24m", 1, 6, 0), - FFACTOR(0, "clk2m", "osc24m", 1, 12, 0), - /* pll cpu */ - FFACTOR(0, "clk1600m", "pll_cpu", 1, 1, CLK_SET_RATE_PARENT), - FFACTOR(0, "clk800m", "pll_cpu", 1, 2, CLK_SET_RATE_PARENT), - /* pll mac */ - FFACTOR(0, "clk25m", "pll_mac", 1, 40, 0), - FFACTOR(0, "clk125m", "pll_mac", 1, 8, 0), - FFACTOR(0, "clk250m", "pll_mac", 1, 4, 0), - FFACTOR(0, "clk50m", "pll_mac", 1, 20, 0), - FFACTOR(0, "clk500m", "pll_mac", 1, 2, 0), - FFACTOR(0, "clk1000m", "pll_mac", 1, 1, 0), - FFACTOR(0, "clk334m", "pll_mac", 1, 3, 0), - FFACTOR(0, "clk167m", "pll_mac", 1, 6, 0), - /* pll mm */ - FFACTOR(0, "clk54m_mm0", "pll_mm0", 1, 22, 0), - FFACTOR(0, "clk74m25", "pll_mm0", 1, 16, 0), - FFACTOR(0, "clk148m5", "pll_mm0", 1, 8, 0), - FFACTOR(0, "clk297m", "pll_mm0", 1, 4, 0), - FFACTOR(0, "clk594m", "pll_mm0", 1, 2, 0), - FFACTOR(0, "pll_mm0_1188m", "pll_mm0", 1, 1, 0), - FFACTOR(0, "clk396m", "pll_mm0", 1, 3, 0), - FFACTOR(0, "clk198m", "pll_mm0", 1, 6, 0), - FFACTOR(0, "clk99m", "pll_mm0", 1, 12, 0), - FFACTOR(0, "clk49m5", "pll_mm0", 1, 24, 0), - /* pll mm */ - FFACTOR(0, "clk324m", "pll_mm1", 1, 4, 0), - FFACTOR(0, "clk648m", "pll_mm1", 1, 2, 0), - FFACTOR(0, "pll_mm1_1296m", "pll_mm1", 1, 1, 0), - FFACTOR(0, "clk216m", "pll_mm1", 1, 6, 0), - FFACTOR(0, "clk432m", "pll_mm1", 1, 3, 0), - FFACTOR(0, "clk108m", "pll_mm1", 1, 12, 0), - FFACTOR(0, "clk72m", "pll_mm1", 1, 18, 0), - FFACTOR(0, "clk27m", "pll_mm1", 1, 48, 0), - FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0), - /* vga */ - FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0), - FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT), - /* pll ddr */ - FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0), - - /* pll audio */ - FFACTOR(0, "pll_audio_1800m", "pll_audio", 1, 1, 0), - FFACTOR(0, "clk32k768", "pll_audio", 1, 27000, 0), - FFACTOR(0, "clk16m384", "pll_audio", 1, 54, 0), - FFACTOR(0, "clk294m", "pll_audio", 1, 3, 0), - - /* pll hsic*/ - FFACTOR(0, "clk240m", "pll_hsic", 1, 4, 0), - FFACTOR(0, "clk480m", "pll_hsic", 1, 2, 0), - FFACTOR(0, "clk192m", "pll_hsic", 1, 5, 0), - FFACTOR(0, "clk_pll_24m", "pll_hsic", 1, 40, 0), - FFACTOR(0, "emmc_mux_div2", "emmc_mux", 1, 2, CLK_SET_RATE_PARENT), -}; - -static const struct clk_div_table noc_div_table[] = { - { .val = 1, .div = 2, }, - { .val = 3, .div = 4, }, -}; -static struct zx_clk_div top_div_clk[] = { - DIV_T(0, "sys_noc_hclk", "sys_noc_aclk", TOP_CLK_DIV0, 0, 2, 0, noc_div_table), - DIV_T(0, "sys_noc_pclk", "sys_noc_aclk", TOP_CLK_DIV0, 4, 2, 0, noc_div_table), -}; - -static struct zx_clk_mux top_mux_clk[] = { - MUX(0, "dbg_mux", dbg_wclk_p, TOP_CLK_MUX0, 12, 2), - MUX(0, "a72_mux", a72_coreclk_p, TOP_CLK_MUX0, 8, 3), - MUX(0, "cpu_peri_mux", cpu_periclk_p, TOP_CLK_MUX0, 4, 3), - MUX_F(0, "a53_mux", a53_coreclk_p, TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0), - MUX(0, "sys_noc_aclk", sys_noc_alck_p, TOP_CLK_MUX1, 0, 3), - MUX(0, "sec_mux", sec_wclk_p, TOP_CLK_MUX2, 16, 3), - MUX(0, "sd1_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 12, 3), - MUX(0, "sd0_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 8, 3), - MUX(0, "emmc_mux", emmc_wclk_p, TOP_CLK_MUX2, 4, 3), - MUX(0, "nand_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 0, 3), - MUX(0, "usb_ref24m_mux", usb_ref24m_p, TOP_CLK_MUX9, 16, 1), - MUX(0, "clk32k", clk32_p, TOP_CLK_MUX9, 12, 1), - MUX_F(0, "wdt_mux", wdt_ares_p, TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0), - MUX(0, "timer_mux", osc, TOP_CLK_MUX9, 4, 1), - MUX(0, "vde_mux", vde_aclk_p, TOP_CLK_MUX4, 0, 3), - MUX(0, "vce_mux", vce_aclk_p, TOP_CLK_MUX4, 4, 3), - MUX(0, "hde_mux", hde_aclk_p, TOP_CLK_MUX4, 8, 3), - MUX(0, "gpu_mux", gpu_aclk_p, TOP_CLK_MUX5, 0, 3), - MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2), - MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3), - MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3), - MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0), - MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3), - MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1), - MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3), - MUX(0, "viu_m1_a_mux", viu_m1_aclk_p, TOP_CLK_MUX6, 4, 3), - MUX(0, "viu_w_mux", viu_clk_p, TOP_CLK_MUX6, 8, 3), - MUX(0, "viu_jpeg_w_mux", viu_jpeg_clk_p, TOP_CLK_MUX6, 12, 3), - MUX(0, "ts_sys_mux", ts_sys_clk_p, TOP_CLK_MUX6, 16, 2), -}; - -static struct zx_clk_gate top_gate_clk[] = { - GATE(CPU_DBG_GATE, "dbg_wclk", "dbg_mux", TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, 0), - GATE(A72_GATE, "a72_coreclk", "a72_mux", TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, 0), - GATE(CPU_PERI_GATE, "cpu_peri", "cpu_peri_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0), - GATE(A53_GATE, "a53_coreclk", "a53_mux", TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, 0), - GATE(SD1_WCLK, "sd1_wclk", "sd1_mux", TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT, 0), - GATE(SD0_WCLK, "sd0_wclk", "sd0_mux", TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, 0), - GATE(EMMC_WCLK, "emmc_wclk", "emmc_mux_div2", TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, 0), - GATE(EMMC_NAND_AXI, "emmc_nand_aclk", "sys_noc_aclk", TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, 0), - GATE(NAND_WCLK, "nand_wclk", "nand_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0), - GATE(EMMC_NAND_AHB, "emmc_nand_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, 0), - GATE(0, "lsp1_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 31, 0, 0), - GATE(LSP1_148M5, "lsp1_148m5", "clk148m5", TOP_CLK_GATE2, 30, 0, 0), - GATE(LSP1_99M, "lsp1_99m", "clk99m", TOP_CLK_GATE2, 29, 0, 0), - GATE(LSP1_24M, "lsp1_24m", "osc24m", TOP_CLK_GATE2, 28, 0, 0), - GATE(LSP0_74M25, "lsp0_74m25", "clk74m25", TOP_CLK_GATE2, 25, 0, 0), - GATE(0, "lsp0_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 24, 0, 0), - GATE(LSP0_32K, "lsp0_32k", "osc32k", TOP_CLK_GATE2, 23, 0, 0), - GATE(LSP0_148M5, "lsp0_148m5", "clk148m5", TOP_CLK_GATE2, 22, 0, 0), - GATE(LSP0_99M, "lsp0_99m", "clk99m", TOP_CLK_GATE2, 21, 0, 0), - GATE(LSP0_24M, "lsp0_24m", "osc24m", TOP_CLK_GATE2, 20, 0, 0), - GATE(AUDIO_99M, "audio_99m", "clk99m", TOP_CLK_GATE5, 27, 0, 0), - GATE(AUDIO_24M, "audio_24m", "osc24m", TOP_CLK_GATE5, 28, 0, 0), - GATE(AUDIO_16M384, "audio_16m384", "clk16m384", TOP_CLK_GATE5, 29, 0, 0), - GATE(AUDIO_32K, "audio_32k", "clk32k", TOP_CLK_GATE5, 30, 0, 0), - GATE(WDT_WCLK, "wdt_wclk", "wdt_mux", TOP_CLK_GATE6, 9, CLK_SET_RATE_PARENT, 0), - GATE(TIMER_WCLK, "timer_wclk", "timer_mux", TOP_CLK_GATE6, 5, CLK_SET_RATE_PARENT, 0), - GATE(VDE_ACLK, "vde_aclk", "vde_mux", TOP_CLK_GATE3, 0, CLK_SET_RATE_PARENT, 0), - GATE(VCE_ACLK, "vce_aclk", "vce_mux", TOP_CLK_GATE3, 4, CLK_SET_RATE_PARENT, 0), - GATE(HDE_ACLK, "hde_aclk", "hde_mux", TOP_CLK_GATE3, 8, CLK_SET_RATE_PARENT, 0), - GATE(GPU_ACLK, "gpu_aclk", "gpu_mux", TOP_CLK_GATE3, 16, CLK_SET_RATE_PARENT, 0), - GATE(SAPPU_ACLK, "sappu_aclk", "sappu_a_mux", TOP_CLK_GATE3, 20, CLK_SET_RATE_PARENT, 0), - GATE(SAPPU_WCLK, "sappu_wclk", "sappu_w_mux", TOP_CLK_GATE3, 22, CLK_SET_RATE_PARENT, 0), - GATE(VOU_ACLK, "vou_aclk", "vou_a_mux", TOP_CLK_GATE4, 16, CLK_SET_RATE_PARENT, 0), - GATE(VOU_MAIN_WCLK, "vou_main_wclk", "vou_main_w_mux", TOP_CLK_GATE4, 18, CLK_SET_RATE_PARENT, 0), - GATE(VOU_AUX_WCLK, "vou_aux_wclk", "vou_aux_w_mux", TOP_CLK_GATE4, 19, CLK_SET_RATE_PARENT, 0), - GATE(VOU_PPU_WCLK, "vou_ppu_wclk", "vou_ppu_w_mux", TOP_CLK_GATE4, 20, CLK_SET_RATE_PARENT, 0), - GATE(MIPI_CFG_CLK, "mipi_cfg_clk", "osc24m", TOP_CLK_GATE4, 21, 0, 0), - GATE(VGA_I2C_WCLK, "vga_i2c_wclk", "vga_i2c_mux", TOP_CLK_GATE4, 23, CLK_SET_RATE_PARENT, 0), - GATE(MIPI_REF_CLK, "mipi_ref_clk", "clk27m", TOP_CLK_GATE4, 24, 0, 0), - GATE(HDMI_OSC_CEC, "hdmi_osc_cec", "clk2m", TOP_CLK_GATE4, 22, 0, 0), - GATE(HDMI_OSC_CLK, "hdmi_osc_clk", "clk240m", TOP_CLK_GATE4, 25, 0, 0), - GATE(HDMI_XCLK, "hdmi_xclk", "osc24m", TOP_CLK_GATE4, 26, 0, 0), - GATE(VIU_M0_ACLK, "viu_m0_aclk", "viu_m0_a_mux", TOP_CLK_GATE4, 0, CLK_SET_RATE_PARENT, 0), - GATE(VIU_M1_ACLK, "viu_m1_aclk", "viu_m1_a_mux", TOP_CLK_GATE4, 1, CLK_SET_RATE_PARENT, 0), - GATE(VIU_WCLK, "viu_wclk", "viu_w_mux", TOP_CLK_GATE4, 2, CLK_SET_RATE_PARENT, 0), - GATE(VIU_JPEG_WCLK, "viu_jpeg_wclk", "viu_jpeg_w_mux", TOP_CLK_GATE4, 3, CLK_SET_RATE_PARENT, 0), - GATE(VIU_CFG_CLK, "viu_cfg_clk", "osc24m", TOP_CLK_GATE4, 6, 0, 0), - GATE(TS_SYS_WCLK, "ts_sys_wclk", "ts_sys_mux", TOP_CLK_GATE5, 2, CLK_SET_RATE_PARENT, 0), - GATE(TS_SYS_108M, "ts_sys_108m", "clk108m", TOP_CLK_GATE5, 3, 0, 0), - GATE(USB20_HCLK, "usb20_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 12, 0, 0), - GATE(USB20_PHY_CLK, "usb20_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 13, 0, 0), - GATE(USB21_HCLK, "usb21_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 14, 0, 0), - GATE(USB21_PHY_CLK, "usb21_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 15, 0, 0), - GATE(GMAC_RMIICLK, "gmac_rmii_clk", "clk50m", TOP_CLK_GATE2, 3, 0, 0), - GATE(GMAC_PCLK, "gmac_pclk", "clk198m", TOP_CLK_GATE2, 1, 0, 0), - GATE(GMAC_ACLK, "gmac_aclk", "clk49m5", TOP_CLK_GATE2, 0, 0, 0), - GATE(GMAC_RFCLK, "gmac_refclk", "clk25m", TOP_CLK_GATE2, 4, 0, 0), - GATE(SD1_AHB, "sd1_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 12, 0, 0), - GATE(SD0_AHB, "sd0_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 8, 0, 0), - GATE(TEMPSENSOR_GATE, "tempsensor_gate", "clk4m", TOP_CLK_GATE5, 31, 0, 0), -}; - -static struct clk_hw_onecell_data top_hw_onecell_data = { - .num = TOP_NR_CLKS, - .hws = { - [TOP_NR_CLKS - 1] = NULL, - }, -}; - -static int __init top_clocks_init(struct device_node *np) -{ - void __iomem *reg_base; - int i, ret; - const char *name; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: Unable to map clk base\n", __func__); - return -ENXIO; - } - - for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) { - zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base; - name = zx296718_pll_clk[i].hw.init->name; - ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw); - if (ret) - pr_warn("top clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) { - if (top_ffactor_clk[i].id) - top_hw_onecell_data.hws[top_ffactor_clk[i].id] = - &top_ffactor_clk[i].factor.hw; - - name = top_ffactor_clk[i].factor.hw.init->name; - ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw); - if (ret) - pr_warn("top clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) { - if (top_mux_clk[i].id) - top_hw_onecell_data.hws[top_mux_clk[i].id] = - &top_mux_clk[i].mux.hw; - - top_mux_clk[i].mux.reg += (uintptr_t)reg_base; - name = top_mux_clk[i].mux.hw.init->name; - ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw); - if (ret) - pr_warn("top clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) { - if (top_gate_clk[i].id) - top_hw_onecell_data.hws[top_gate_clk[i].id] = - &top_gate_clk[i].gate.hw; - - top_gate_clk[i].gate.reg += (uintptr_t)reg_base; - name = top_gate_clk[i].gate.hw.init->name; - ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw); - if (ret) - pr_warn("top clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) { - if (top_div_clk[i].id) - top_hw_onecell_data.hws[top_div_clk[i].id] = - &top_div_clk[i].div.hw; - - top_div_clk[i].div.reg += (uintptr_t)reg_base; - name = top_div_clk[i].div.hw.init->name; - ret = clk_hw_register(NULL, &top_div_clk[i].div.hw); - if (ret) - pr_warn("top clk %s init error!\n", name); - } - - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - &top_hw_onecell_data); - if (ret) { - pr_err("failed to register top clk provider: %d\n", ret); - return ret; - } - - return 0; -} - -static const struct clk_div_table common_even_div_table[] = { - { .val = 0, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 3, .div = 4, }, - { .val = 5, .div = 6, }, - { .val = 7, .div = 8, }, - { .val = 9, .div = 10, }, - { .val = 11, .div = 12, }, - { .val = 13, .div = 14, }, - { .val = 15, .div = 16, }, -}; - -static const struct clk_div_table common_div_table[] = { - { .val = 0, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 2, .div = 3, }, - { .val = 3, .div = 4, }, - { .val = 4, .div = 5, }, - { .val = 5, .div = 6, }, - { .val = 6, .div = 7, }, - { .val = 7, .div = 8, }, - { .val = 8, .div = 9, }, - { .val = 9, .div = 10, }, - { .val = 10, .div = 11, }, - { .val = 11, .div = 12, }, - { .val = 12, .div = 13, }, - { .val = 13, .div = 14, }, - { .val = 14, .div = 15, }, - { .val = 15, .div = 16, }, -}; - -PNAME(lsp0_wclk_common_p) = { - "lsp0_24m", - "lsp0_99m", -}; - -PNAME(lsp0_wclk_timer3_p) = { - "timer3_div", - "lsp0_32k" -}; - -PNAME(lsp0_wclk_timer4_p) = { - "timer4_div", - "lsp0_32k" -}; - -PNAME(lsp0_wclk_timer5_p) = { - "timer5_div", - "lsp0_32k" -}; - -PNAME(lsp0_wclk_spifc0_p) = { - "lsp0_148m5", - "lsp0_24m", - "lsp0_99m", - "lsp0_74m25" -}; - -PNAME(lsp0_wclk_ssp_p) = { - "lsp0_148m5", - "lsp0_99m", - "lsp0_24m", -}; - -static struct zx_clk_mux lsp0_mux_clk[] = { - MUX(0, "timer3_wclk_mux", lsp0_wclk_timer3_p, LSP0_TIMER3_CLK, 4, 1), - MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1), - MUX(0, "timer5_wclk_mux", lsp0_wclk_timer5_p, LSP0_TIMER5_CLK, 4, 1), - MUX(0, "uart3_wclk_mux", lsp0_wclk_common_p, LSP0_UART3_CLK, 4, 1), - MUX(0, "uart1_wclk_mux", lsp0_wclk_common_p, LSP0_UART1_CLK, 4, 1), - MUX(0, "uart2_wclk_mux", lsp0_wclk_common_p, LSP0_UART2_CLK, 4, 1), - MUX(0, "spifc0_wclk_mux", lsp0_wclk_spifc0_p, LSP0_SPIFC0_CLK, 4, 2), - MUX(0, "i2c4_wclk_mux", lsp0_wclk_common_p, LSP0_I2C4_CLK, 4, 1), - MUX(0, "i2c5_wclk_mux", lsp0_wclk_common_p, LSP0_I2C5_CLK, 4, 1), - MUX(0, "ssp0_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP0_CLK, 4, 1), - MUX(0, "ssp1_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP1_CLK, 4, 1), - MUX(0, "i2c3_wclk_mux", lsp0_wclk_common_p, LSP0_I2C3_CLK, 4, 1), -}; - -static struct zx_clk_gate lsp0_gate_clk[] = { - GATE(LSP0_TIMER3_WCLK, "timer3_wclk", "timer3_wclk_mux", LSP0_TIMER3_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_TIMER5_WCLK, "timer5_wclk", "timer5_wclk_mux", LSP0_TIMER5_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_UART3_WCLK, "uart3_wclk", "uart3_wclk_mux", LSP0_UART3_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_UART1_WCLK, "uart1_wclk", "uart1_wclk_mux", LSP0_UART1_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_UART2_WCLK, "uart2_wclk", "uart2_wclk_mux", LSP0_UART2_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_SPIFC0_WCLK, "spifc0_wclk", "spifc0_wclk_mux", LSP0_SPIFC0_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_I2C4_WCLK, "i2c4_wclk", "i2c4_wclk_mux", LSP0_I2C4_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_I2C5_WCLK, "i2c5_wclk", "i2c5_wclk_mux", LSP0_I2C5_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_SSP0_WCLK, "ssp0_wclk", "ssp0_div", LSP0_SSP0_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_SSP1_WCLK, "ssp1_wclk", "ssp1_div", LSP0_SSP1_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP0_I2C3_WCLK, "i2c3_wclk", "i2c3_wclk_mux", LSP0_I2C3_CLK, 1, CLK_SET_RATE_PARENT, 0), -}; - -static struct zx_clk_div lsp0_div_clk[] = { - DIV_T(0, "timer3_div", "lsp0_24m", LSP0_TIMER3_CLK, 12, 4, 0, common_even_div_table), - DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK, 12, 4, 0, common_even_div_table), - DIV_T(0, "timer5_div", "lsp0_24m", LSP0_TIMER5_CLK, 12, 4, 0, common_even_div_table), - DIV_T(0, "ssp0_div", "ssp0_wclk_mux", LSP0_SSP0_CLK, 12, 4, 0, common_even_div_table), - DIV_T(0, "ssp1_div", "ssp1_wclk_mux", LSP0_SSP1_CLK, 12, 4, 0, common_even_div_table), -}; - -static struct clk_hw_onecell_data lsp0_hw_onecell_data = { - .num = LSP0_NR_CLKS, - .hws = { - [LSP0_NR_CLKS - 1] = NULL, - }, -}; - -static int __init lsp0_clocks_init(struct device_node *np) -{ - void __iomem *reg_base; - int i, ret; - const char *name; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: Unable to map clk base\n", __func__); - return -ENXIO; - } - - for (i = 0; i < ARRAY_SIZE(lsp0_mux_clk); i++) { - if (lsp0_mux_clk[i].id) - lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] = - &lsp0_mux_clk[i].mux.hw; - - lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base; - name = lsp0_mux_clk[i].mux.hw.init->name; - ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw); - if (ret) - pr_warn("lsp0 clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) { - if (lsp0_gate_clk[i].id) - lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] = - &lsp0_gate_clk[i].gate.hw; - - lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base; - name = lsp0_gate_clk[i].gate.hw.init->name; - ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw); - if (ret) - pr_warn("lsp0 clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) { - if (lsp0_div_clk[i].id) - lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] = - &lsp0_div_clk[i].div.hw; - - lsp0_div_clk[i].div.reg += (uintptr_t)reg_base; - name = lsp0_div_clk[i].div.hw.init->name; - ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw); - if (ret) - pr_warn("lsp0 clk %s init error!\n", name); - } - - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - &lsp0_hw_onecell_data); - if (ret) { - pr_err("failed to register lsp0 clk provider: %d\n", ret); - return ret; - } - - return 0; -} - -PNAME(lsp1_wclk_common_p) = { - "lsp1_24m", - "lsp1_99m", -}; - -PNAME(lsp1_wclk_ssp_p) = { - "lsp1_148m5", - "lsp1_99m", - "lsp1_24m", -}; - -static struct zx_clk_mux lsp1_mux_clk[] = { - MUX(0, "uart4_wclk_mux", lsp1_wclk_common_p, LSP1_UART4_CLK, 4, 1), - MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1), - MUX(0, "pwm_wclk_mux", lsp1_wclk_common_p, LSP1_PWM_CLK, 4, 1), - MUX(0, "i2c2_wclk_mux", lsp1_wclk_common_p, LSP1_I2C2_CLK, 4, 1), - MUX(0, "ssp2_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP2_CLK, 4, 2), - MUX(0, "ssp3_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP3_CLK, 4, 2), - MUX(0, "ssp4_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP4_CLK, 4, 2), - MUX(0, "usim1_wclk_mux", lsp1_wclk_common_p, LSP1_USIM1_CLK, 4, 1), -}; - -static struct zx_clk_div lsp1_div_clk[] = { - DIV_T(0, "pwm_div", "pwm_wclk_mux", LSP1_PWM_CLK, 12, 4, CLK_SET_RATE_PARENT, common_div_table), - DIV_T(0, "ssp2_div", "ssp2_wclk_mux", LSP1_SSP2_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table), - DIV_T(0, "ssp3_div", "ssp3_wclk_mux", LSP1_SSP3_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table), - DIV_T(0, "ssp4_div", "ssp4_wclk_mux", LSP1_SSP4_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table), -}; - -static struct zx_clk_gate lsp1_gate_clk[] = { - GATE(LSP1_UART4_WCLK, "lsp1_uart4_wclk", "uart4_wclk_mux", LSP1_UART4_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP1_PWM_WCLK, "lsp1_pwm_wclk", "pwm_div", LSP1_PWM_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP1_PWM_PCLK, "lsp1_pwm_pclk", "lsp1_pclk", LSP1_PWM_CLK, 0, 0, 0), - GATE(LSP1_I2C2_WCLK, "lsp1_i2c2_wclk", "i2c2_wclk_mux", LSP1_I2C2_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP1_SSP2_WCLK, "lsp1_ssp2_wclk", "ssp2_div", LSP1_SSP2_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP1_SSP3_WCLK, "lsp1_ssp3_wclk", "ssp3_div", LSP1_SSP3_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP1_SSP4_WCLK, "lsp1_ssp4_wclk", "ssp4_div", LSP1_SSP4_CLK, 1, CLK_SET_RATE_PARENT, 0), - GATE(LSP1_USIM1_WCLK, "lsp1_usim1_wclk", "usim1_wclk_mux", LSP1_USIM1_CLK, 1, CLK_SET_RATE_PARENT, 0), -}; - -static struct clk_hw_onecell_data lsp1_hw_onecell_data = { - .num = LSP1_NR_CLKS, - .hws = { - [LSP1_NR_CLKS - 1] = NULL, - }, -}; - -static int __init lsp1_clocks_init(struct device_node *np) -{ - void __iomem *reg_base; - int i, ret; - const char *name; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: Unable to map clk base\n", __func__); - return -ENXIO; - } - - for (i = 0; i < ARRAY_SIZE(lsp1_mux_clk); i++) { - if (lsp1_mux_clk[i].id) - lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] = - &lsp0_mux_clk[i].mux.hw; - - lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base; - name = lsp1_mux_clk[i].mux.hw.init->name; - ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw); - if (ret) - pr_warn("lsp1 clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) { - if (lsp1_gate_clk[i].id) - lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] = - &lsp1_gate_clk[i].gate.hw; - - lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base; - name = lsp1_gate_clk[i].gate.hw.init->name; - ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw); - if (ret) - pr_warn("lsp1 clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) { - if (lsp1_div_clk[i].id) - lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] = - &lsp1_div_clk[i].div.hw; - - lsp1_div_clk[i].div.reg += (uintptr_t)reg_base; - name = lsp1_div_clk[i].div.hw.init->name; - ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw); - if (ret) - pr_warn("lsp1 clk %s init error!\n", name); - } - - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - &lsp1_hw_onecell_data); - if (ret) { - pr_err("failed to register lsp1 clk provider: %d\n", ret); - return ret; - } - - return 0; -} - -PNAME(audio_wclk_common_p) = { - "audio_99m", - "audio_24m", -}; - -PNAME(audio_timer_p) = { - "audio_24m", - "audio_32k", -}; - -static struct zx_clk_mux audio_mux_clk[] = { - MUX(I2S0_WCLK_MUX, "i2s0_wclk_mux", audio_wclk_common_p, AUDIO_I2S0_CLK, 0, 1), - MUX(I2S1_WCLK_MUX, "i2s1_wclk_mux", audio_wclk_common_p, AUDIO_I2S1_CLK, 0, 1), - MUX(I2S2_WCLK_MUX, "i2s2_wclk_mux", audio_wclk_common_p, AUDIO_I2S2_CLK, 0, 1), - MUX(I2S3_WCLK_MUX, "i2s3_wclk_mux", audio_wclk_common_p, AUDIO_I2S3_CLK, 0, 1), - MUX(0, "i2c0_wclk_mux", audio_wclk_common_p, AUDIO_I2C0_CLK, 0, 1), - MUX(0, "spdif0_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF0_CLK, 0, 1), - MUX(0, "spdif1_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF1_CLK, 0, 1), - MUX(0, "timer_wclk_mux", audio_timer_p, AUDIO_TIMER_CLK, 0, 1), -}; - -static struct clk_zx_audio_divider audio_adiv_clk[] = { - AUDIO_DIV(0, "i2s0_wclk_div", "i2s0_wclk_mux", AUDIO_I2S0_DIV_CFG1), - AUDIO_DIV(0, "i2s1_wclk_div", "i2s1_wclk_mux", AUDIO_I2S1_DIV_CFG1), - AUDIO_DIV(0, "i2s2_wclk_div", "i2s2_wclk_mux", AUDIO_I2S2_DIV_CFG1), - AUDIO_DIV(0, "i2s3_wclk_div", "i2s3_wclk_mux", AUDIO_I2S3_DIV_CFG1), - AUDIO_DIV(0, "spdif0_wclk_div", "spdif0_wclk_mux", AUDIO_SPDIF0_DIV_CFG1), - AUDIO_DIV(0, "spdif1_wclk_div", "spdif1_wclk_mux", AUDIO_SPDIF1_DIV_CFG1), -}; - -static struct zx_clk_div audio_div_clk[] = { - DIV_T(0, "tdm_wclk_div", "audio_16m384", AUDIO_TDM_CLK, 8, 4, 0, common_div_table), -}; - -static struct zx_clk_gate audio_gate_clk[] = { - GATE(AUDIO_I2S0_WCLK, "i2s0_wclk", "i2s0_wclk_div", AUDIO_I2S0_CLK, 9, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0), - GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0), - GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0), - GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0), - GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17, CLK_SET_RATE_PARENT, 0), - GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0, 0), -}; - -static struct clk_hw_onecell_data audio_hw_onecell_data = { - .num = AUDIO_NR_CLKS, - .hws = { - [AUDIO_NR_CLKS - 1] = NULL, - }, -}; - -static int __init audio_clocks_init(struct device_node *np) -{ - void __iomem *reg_base; - int i, ret; - const char *name; - - reg_base = of_iomap(np, 0); - if (!reg_base) { - pr_err("%s: Unable to map audio clk base\n", __func__); - return -ENXIO; - } - - for (i = 0; i < ARRAY_SIZE(audio_mux_clk); i++) { - if (audio_mux_clk[i].id) - audio_hw_onecell_data.hws[audio_mux_clk[i].id] = - &audio_mux_clk[i].mux.hw; - - audio_mux_clk[i].mux.reg += (uintptr_t)reg_base; - name = audio_mux_clk[i].mux.hw.init->name; - ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw); - if (ret) - pr_warn("audio clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) { - if (audio_adiv_clk[i].id) - audio_hw_onecell_data.hws[audio_adiv_clk[i].id] = - &audio_adiv_clk[i].hw; - - audio_adiv_clk[i].reg_base += (uintptr_t)reg_base; - name = audio_adiv_clk[i].hw.init->name; - ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw); - if (ret) - pr_warn("audio clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) { - if (audio_div_clk[i].id) - audio_hw_onecell_data.hws[audio_div_clk[i].id] = - &audio_div_clk[i].div.hw; - - audio_div_clk[i].div.reg += (uintptr_t)reg_base; - name = audio_div_clk[i].div.hw.init->name; - ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw); - if (ret) - pr_warn("audio clk %s init error!\n", name); - } - - for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) { - if (audio_gate_clk[i].id) - audio_hw_onecell_data.hws[audio_gate_clk[i].id] = - &audio_gate_clk[i].gate.hw; - - audio_gate_clk[i].gate.reg += (uintptr_t)reg_base; - name = audio_gate_clk[i].gate.hw.init->name; - ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw); - if (ret) - pr_warn("audio clk %s init error!\n", name); - } - - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - &audio_hw_onecell_data); - if (ret) { - pr_err("failed to register audio clk provider: %d\n", ret); - return ret; - } - - return 0; -} - -static const struct of_device_id zx_clkc_match_table[] = { - { .compatible = "zte,zx296718-topcrm", .data = &top_clocks_init }, - { .compatible = "zte,zx296718-lsp0crm", .data = &lsp0_clocks_init }, - { .compatible = "zte,zx296718-lsp1crm", .data = &lsp1_clocks_init }, - { .compatible = "zte,zx296718-audiocrm", .data = &audio_clocks_init }, - { } -}; - -static int zx_clkc_probe(struct platform_device *pdev) -{ - int (*init_fn)(struct device_node *np); - struct device_node *np = pdev->dev.of_node; - - init_fn = of_device_get_match_data(&pdev->dev); - if (!init_fn) { - dev_err(&pdev->dev, "Error: No device match found\n"); - return -ENODEV; - } - - return init_fn(np); -} - -static struct platform_driver zx_clk_driver = { - .probe = zx_clkc_probe, - .driver = { - .name = "zx296718-clkc", - .of_match_table = zx_clkc_match_table, - }, -}; - -static int __init zx_clk_init(void) -{ - return platform_driver_register(&zx_clk_driver); -} -core_initcall(zx_clk_init); diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c deleted file mode 100644 index 8bda6d41ad3a..000000000000 --- a/drivers/clk/zte/clk.c +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2014 Linaro Ltd. - * Copyright (C) 2014 ZTE Corporation. - */ - -#include <linux/clk-provider.h> -#include <linux/err.h> -#include <linux/gcd.h> -#include <linux/io.h> -#include <linux/iopoll.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include <asm/div64.h> - -#include "clk.h" - -#define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw) -#define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw) - -#define CFG0_CFG1_OFFSET 4 -#define LOCK_FLAG 30 -#define POWER_DOWN 31 - -static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate) -{ - const struct zx_pll_config *config = zx_pll->lookup_table; - int i; - - for (i = 0; i < zx_pll->count; i++) { - if (config[i].rate > rate) - return i > 0 ? i - 1 : 0; - - if (config[i].rate == rate) - return i; - } - - return i - 1; -} - -static int hw_to_idx(struct clk_zx_pll *zx_pll) -{ - const struct zx_pll_config *config = zx_pll->lookup_table; - u32 hw_cfg0, hw_cfg1; - int i; - - hw_cfg0 = readl_relaxed(zx_pll->reg_base); - hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); - - /* For matching the value in lookup table */ - hw_cfg0 &= ~BIT(zx_pll->lock_bit); - - /* Check availability of pd_bit */ - if (zx_pll->pd_bit < 32) - hw_cfg0 |= BIT(zx_pll->pd_bit); - - for (i = 0; i < zx_pll->count; i++) { - if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) - return i; - } - - return -EINVAL; -} - -static unsigned long zx_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); - int idx; - - idx = hw_to_idx(zx_pll); - if (unlikely(idx == -EINVAL)) - return 0; - - return zx_pll->lookup_table[idx].rate; -} - -static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); - int idx; - - idx = rate_to_idx(zx_pll, rate); - - return zx_pll->lookup_table[idx].rate; -} - -static int zx_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - /* Assume current cpu is not running on current PLL */ - struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); - const struct zx_pll_config *config; - int idx; - - idx = rate_to_idx(zx_pll, rate); - config = &zx_pll->lookup_table[idx]; - - writel_relaxed(config->cfg0, zx_pll->reg_base); - writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); - - return 0; -} - -static int zx_pll_enable(struct clk_hw *hw) -{ - struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); - u32 reg; - - /* If pd_bit is not available, simply return success. */ - if (zx_pll->pd_bit > 31) - return 0; - - reg = readl_relaxed(zx_pll->reg_base); - writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); - - return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, - reg & BIT(zx_pll->lock_bit), 0, 100); -} - -static void zx_pll_disable(struct clk_hw *hw) -{ - struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); - u32 reg; - - if (zx_pll->pd_bit > 31) - return; - - reg = readl_relaxed(zx_pll->reg_base); - writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); -} - -static int zx_pll_is_enabled(struct clk_hw *hw) -{ - struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); - u32 reg; - - reg = readl_relaxed(zx_pll->reg_base); - - return !(reg & BIT(zx_pll->pd_bit)); -} - -const struct clk_ops zx_pll_ops = { - .recalc_rate = zx_pll_recalc_rate, - .round_rate = zx_pll_round_rate, - .set_rate = zx_pll_set_rate, - .enable = zx_pll_enable, - .disable = zx_pll_disable, - .is_enabled = zx_pll_is_enabled, -}; -EXPORT_SYMBOL(zx_pll_ops); - -struct clk *clk_register_zx_pll(const char *name, const char *parent_name, - unsigned long flags, void __iomem *reg_base, - const struct zx_pll_config *lookup_table, - int count, spinlock_t *lock) -{ - struct clk_zx_pll *zx_pll; - struct clk *clk; - struct clk_init_data init; - - zx_pll = kzalloc(sizeof(*zx_pll), GFP_KERNEL); - if (!zx_pll) - return ERR_PTR(-ENOMEM); - - init.name = name; - init.ops = &zx_pll_ops; - init.flags = flags; - init.parent_names = parent_name ? &parent_name : NULL; - init.num_parents = parent_name ? 1 : 0; - - zx_pll->reg_base = reg_base; - zx_pll->lookup_table = lookup_table; - zx_pll->count = count; - zx_pll->lock_bit = LOCK_FLAG; - zx_pll->pd_bit = POWER_DOWN; - zx_pll->lock = lock; - zx_pll->hw.init = &init; - - clk = clk_register(NULL, &zx_pll->hw); - if (IS_ERR(clk)) - kfree(zx_pll); - - return clk; -} - -#define BPAR 1000000 -static u32 calc_reg(u32 parent_rate, u32 rate) -{ - u32 sel, integ, fra_div, tmp; - u64 tmp64 = (u64)parent_rate * BPAR; - - do_div(tmp64, rate); - integ = (u32)tmp64 / BPAR; - integ = integ >> 1; - - tmp = (u32)tmp64 % BPAR; - sel = tmp / BPAR; - - tmp = tmp % BPAR; - fra_div = tmp * 0xff / BPAR; - tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div; - - /* Set I2S integer divider as 1. This bit is reserved for SPDIF - * and do no harm. - */ - tmp |= BIT(28); - return tmp; -} - -static u32 calc_rate(u32 reg, u32 parent_rate) -{ - u32 sel, integ, fra_div, tmp; - u64 tmp64 = (u64)parent_rate * BPAR; - - tmp = reg; - sel = (tmp >> 24) & BIT(0); - integ = (tmp >> 16) & 0xff; - fra_div = tmp & 0xff; - - tmp = fra_div * BPAR; - tmp = tmp / 0xff; - tmp += sel * BPAR; - tmp += 2 * integ * BPAR; - do_div(tmp64, tmp); - - return (u32)tmp64; -} - -static unsigned long zx_audio_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); - u32 reg; - - reg = readl_relaxed(zx_audio->reg_base); - return calc_rate(reg, parent_rate); -} - -static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - u32 reg; - - if (rate * 2 > *prate) - return -EINVAL; - - reg = calc_reg(*prate, rate); - return calc_rate(reg, *prate); -} - -static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); - u32 reg; - - reg = calc_reg(parent_rate, rate); - writel_relaxed(reg, zx_audio->reg_base); - - return 0; -} - -#define ZX_AUDIO_EN BIT(25) -static int zx_audio_enable(struct clk_hw *hw) -{ - struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); - u32 reg; - - reg = readl_relaxed(zx_audio->reg_base); - writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base); - return 0; -} - -static void zx_audio_disable(struct clk_hw *hw) -{ - struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw); - u32 reg; - - reg = readl_relaxed(zx_audio->reg_base); - writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base); -} - -static const struct clk_ops zx_audio_ops = { - .recalc_rate = zx_audio_recalc_rate, - .round_rate = zx_audio_round_rate, - .set_rate = zx_audio_set_rate, - .enable = zx_audio_enable, - .disable = zx_audio_disable, -}; - -struct clk *clk_register_zx_audio(const char *name, - const char * const parent_name, - unsigned long flags, - void __iomem *reg_base) -{ - struct clk_zx_audio *zx_audio; - struct clk *clk; - struct clk_init_data init; - - zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL); - if (!zx_audio) - return ERR_PTR(-ENOMEM); - - init.name = name; - init.ops = &zx_audio_ops; - init.flags = flags; - init.parent_names = parent_name ? &parent_name : NULL; - init.num_parents = parent_name ? 1 : 0; - - zx_audio->reg_base = reg_base; - zx_audio->hw.init = &init; - - clk = clk_register(NULL, &zx_audio->hw); - if (IS_ERR(clk)) - kfree(zx_audio); - - return clk; -} - -#define CLK_AUDIO_DIV_FRAC BIT(0) -#define CLK_AUDIO_DIV_INT BIT(1) -#define CLK_AUDIO_DIV_UNCOMMON BIT(1) - -#define CLK_AUDIO_DIV_FRAC_NSHIFT 16 -#define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16) -#define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff) -#define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2) -#define CLK_AUDIO_DIV_INT_INT_SHIFT 24 -#define CLK_AUDIO_DIV_INT_INT_WIDTH 4 - -struct zx_clk_audio_div_table { - unsigned long rate; - unsigned int int_reg; - unsigned int frac_reg; -}; - -#define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw) - -static unsigned long audio_calc_rate(struct clk_zx_audio_divider *audio_div, - u32 reg_frac, u32 reg_int, - unsigned long parent_rate) -{ - unsigned long rate, m, n; - - m = reg_frac & 0xffff; - n = (reg_frac >> 16) & 0xffff; - - m = (reg_int & 0xffff) * n + m; - rate = (parent_rate * n) / m; - - return rate; -} - -static void audio_calc_reg(struct clk_zx_audio_divider *audio_div, - struct zx_clk_audio_div_table *div_table, - unsigned long rate, unsigned long parent_rate) -{ - unsigned int reg_int, reg_frac; - unsigned long m, n, div; - - reg_int = parent_rate / rate; - - if (reg_int > CLK_AUDIO_DIV_INT_FRAC_MAX) - reg_int = CLK_AUDIO_DIV_INT_FRAC_MAX; - else if (reg_int < CLK_AUDIO_DIV_INT_FRAC_MIN) - reg_int = 0; - m = parent_rate - rate * reg_int; - n = rate; - - div = gcd(m, n); - m = m / div; - n = n / div; - - if ((m >> 16) || (n >> 16)) { - if (m > n) { - n = n * 0xffff / m; - m = 0xffff; - } else { - m = m * 0xffff / n; - n = 0xffff; - } - } - reg_frac = m | (n << 16); - - div_table->rate = parent_rate * n / (reg_int * n + m); - div_table->int_reg = reg_int; - div_table->frac_reg = reg_frac; -} - -static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw); - u32 reg_frac, reg_int; - - reg_frac = readl_relaxed(zx_audio_div->reg_base); - reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4); - - return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate); -} - -static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw); - struct zx_clk_audio_div_table divt; - - audio_calc_reg(zx_audio_div, &divt, rate, *prate); - - return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate); -} - -static int zx_audio_div_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw); - struct zx_clk_audio_div_table divt; - unsigned int val; - - audio_calc_reg(zx_audio_div, &divt, rate, parent_rate); - if (divt.rate != rate) - pr_debug("the real rate is:%ld", divt.rate); - - writel_relaxed(divt.frac_reg, zx_audio_div->reg_base); - - val = readl_relaxed(zx_audio_div->reg_base + 0x4); - val &= ~0xffff; - val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE; - writel_relaxed(val, zx_audio_div->reg_base + 0x4); - - mdelay(1); - - val = readl_relaxed(zx_audio_div->reg_base + 0x4); - val &= ~CLK_AUDIO_DIV_INT_FRAC_RE; - writel_relaxed(val, zx_audio_div->reg_base + 0x4); - - return 0; -} - -const struct clk_ops zx_audio_div_ops = { - .recalc_rate = zx_audio_div_recalc_rate, - .round_rate = zx_audio_div_round_rate, - .set_rate = zx_audio_div_set_rate, -}; diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h deleted file mode 100644 index aeaf2a380ba6..000000000000 --- a/drivers/clk/zte/clk.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Ltd. - * Copyright (C) 2014 ZTE Corporation. - */ - -#ifndef __ZTE_CLK_H -#define __ZTE_CLK_H -#include <linux/clk-provider.h> -#include <linux/spinlock.h> - -#define PNAME(x) static const char *x[] - -struct zx_pll_config { - unsigned long rate; - u32 cfg0; - u32 cfg1; -}; - -struct clk_zx_pll { - struct clk_hw hw; - void __iomem *reg_base; - const struct zx_pll_config *lookup_table; /* order by rate asc */ - int count; - spinlock_t *lock; - u8 pd_bit; /* power down bit */ - u8 lock_bit; /* pll lock flag bit */ -}; - -#define PLL_RATE(_rate, _cfg0, _cfg1) \ -{ \ - .rate = _rate, \ - .cfg0 = _cfg0, \ - .cfg1 = _cfg1, \ -} - -#define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ -{ \ - .reg_base = (void __iomem *) _reg, \ - .lookup_table = _table, \ - .count = ARRAY_SIZE(_table), \ - .pd_bit = _pd, \ - .lock_bit = _lock, \ - .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \ - CLK_GET_RATE_NOCACHE), \ -} - -/* - * The pd_bit is not available on ZX296718, so let's pass something - * bigger than 31, e.g. 0xff, to indicate that. - */ -#define ZX296718_PLL(_name, _parent, _reg, _table) \ -ZX_PLL(_name, _parent, _reg, _table, 0xff, 30) - -struct zx_clk_gate { - struct clk_gate gate; - u16 id; -}; - -#define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ -{ \ - .gate = { \ - .reg = (void __iomem *) _reg, \ - .bit_idx = (_bit), \ - .flags = _gflags, \ - .lock = &clk_lock, \ - .hw.init = CLK_HW_INIT(_name, \ - _parent, \ - &clk_gate_ops, \ - _flag | CLK_IGNORE_UNUSED), \ - }, \ - .id = _id, \ -} - -struct zx_clk_fixed_factor { - struct clk_fixed_factor factor; - u16 id; -}; - -#define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ -{ \ - .factor = { \ - .div = _div, \ - .mult = _mult, \ - .hw.init = CLK_HW_INIT(_name, \ - _parent, \ - &clk_fixed_factor_ops, \ - _flag), \ - }, \ - .id = _id, \ -} - -struct zx_clk_mux { - struct clk_mux mux; - u16 id; -}; - -#define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ -{ \ - .mux = { \ - .reg = (void __iomem *) _reg, \ - .mask = BIT(_width) - 1, \ - .shift = _shift, \ - .flags = _mflag, \ - .lock = &clk_lock, \ - .hw.init = CLK_HW_INIT_PARENTS(_name, \ - _parent, \ - &clk_mux_ops, \ - _flag), \ - }, \ - .id = _id, \ -} - -#define MUX(_id, _name, _parent, _reg, _shift, _width) \ -MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0) - -struct zx_clk_div { - struct clk_divider div; - u16 id; -}; - -#define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ -{ \ - .div = { \ - .reg = (void __iomem *) _reg, \ - .shift = _shift, \ - .width = _width, \ - .flags = 0, \ - .table = _table, \ - .lock = &clk_lock, \ - .hw.init = CLK_HW_INIT(_name, \ - _parent, \ - &clk_divider_ops, \ - _flag), \ - }, \ - .id = _id, \ -} - -struct clk_zx_audio_divider { - struct clk_hw hw; - void __iomem *reg_base; - unsigned int rate_count; - spinlock_t *lock; - u16 id; -}; - -#define AUDIO_DIV(_id, _name, _parent, _reg) \ -{ \ - .reg_base = (void __iomem *) _reg, \ - .lock = &clk_lock, \ - .hw.init = CLK_HW_INIT(_name, \ - _parent, \ - &zx_audio_div_ops, \ - 0), \ - .id = _id, \ -} - -struct clk *clk_register_zx_pll(const char *name, const char *parent_name, - unsigned long flags, void __iomem *reg_base, - const struct zx_pll_config *lookup_table, int count, spinlock_t *lock); - -struct clk_zx_audio { - struct clk_hw hw; - void __iomem *reg_base; -}; - -struct clk *clk_register_zx_audio(const char *name, - const char * const parent_name, - unsigned long flags, void __iomem *reg_base); - -extern const struct clk_ops zx_pll_ops; -extern const struct clk_ops zx_audio_div_ops; - -#endif |