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authorchunhui dai <chunhui.dai@mediatek.com>2019-02-25 10:09:10 +0800
committerStephen Boyd <sboyd@kernel.org>2019-02-25 09:19:33 -0800
commitd3174bc836d5aadc871f74ed496694c5ea27b104 (patch)
tree750508a5799b4feb87b03fd40c6703680cbf3cfe /drivers/clk
parentb026a7eca1a7b1254017835f91438b569bfc4e54 (diff)
downloadlinux-d3174bc836d5aadc871f74ed496694c5ea27b104.tar.bz2
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF. Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> Signed-off-by: wangyan wang <wangyan.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index ab6ab07f53e6..905a2316f6a7 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = {
0x0080, 8, 2, 15),
MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
0x0080, 16, 3, 23),
- MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
- 0x0080, 24, 2, 31),
+ MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
+ 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
0x0090, 0, 3, 7),