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authorStephen Boyd <sboyd@kernel.org>2019-03-29 15:42:34 -0700
committerStephen Boyd <sboyd@kernel.org>2019-03-29 15:42:34 -0700
commit9f842abde84d4232d7a1951952dc148bd83f9ada (patch)
tree94084fbf8b811aa0e94818730c92ef99f6f826d8 /drivers/clk
parent22cf7c6f8ee69794c78fb4b846bd95ea065ce079 (diff)
parent6620f45ff8519549a6877663f965c10002918dc2 (diff)
downloadlinux-9f842abde84d4232d7a1951952dc148bd83f9ada.tar.bz2
Merge tag 'meson-clk-fixes-for-5.1-v2' of https://github.com/BayLibre/clk-meson into clk-fixes
Pull more fixes for meson clocks from Neil Armstrong: - clk-pll: fix rate rounding fixing meson8b boot failure - vid-pll-div: fix recal_rate warning and return when invalid setting * tag 'meson-clk-fixes-for-5.1-v2' of https://github.com/BayLibre/clk-meson: clk: meson: vid-pll-div: remove warning and return 0 on invalid config clk: meson: pll: fix rounding and setting a rate that matches precisely
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/meson/clk-pll.c2
-rw-r--r--drivers/clk/meson/vid-pll-div.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 41e16dd7272a..7a14ac9b2fec 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -120,7 +120,7 @@ static bool meson_clk_pll_is_better(unsigned long rate,
return true;
} else {
/* Round down */
- if (now < rate && best < now)
+ if (now <= rate && best < now)
return true;
}
diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-div.c
index 08bcc01c0923..daff235bc763 100644
--- a/drivers/clk/meson/vid-pll-div.c
+++ b/drivers/clk/meson/vid-pll-div.c
@@ -82,8 +82,8 @@ static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw,
div = _get_table_val(meson_parm_read(clk->map, &pll_div->val),
meson_parm_read(clk->map, &pll_div->sel));
if (!div || !div->divider) {
- pr_info("%s: Invalid config value for vid_pll_div\n", __func__);
- return parent_rate;
+ pr_debug("%s: Invalid config value for vid_pll_div\n", __func__);
+ return 0;
}
return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);